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參數(shù)資料
| 型號(hào)： | AMPAL22V10 |
| 廠商： | Advanced Micro Devices, Inc. |
| 元件分類： | PAL |
| 英文描述： | PAL22V10 Family, AmPAL22V10/A 24-Pin TTL Versatile PAL Device |
| 中文描述： | PAL22V10家庭，AmPAL22V10 / 24針的TTL多功能PAL制式設(shè)備 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 184K |
| 代理商： | AMPAL22V10 |
AMD
2-200
PAL22V10 Family
FUNCTIONAL DESCRIPTION
The PAL22V10 allows the systems engineer to imple-
ment a design on-chip, by opening fuse links to config-
ure AND and OR gates within the device, according to
the desired logic function. Complex interconnections
between gates, which previously required time-
consuming layout, are lifted from the PC board and
placed on silicon, where they can be easily modified dur-
ing prototyping or production.
Product terms with all fuses opened assume the logical
HIGH state; product terms connected to both true and
complement of any single input assume the logical LOW
state.
The PAL22V10 has 12 inputs and 10 I/O macrocells.
The macrocell (Figure 1) allows one of four potential out-
put configurations; registered output or combinatorial
I/O, active high or active low (see Figure 2). The configu-
ration choice is made according to the user’s design
specification and corresponding programming of the
configuration bits S
0
– S
1
. Multiplexer controls initially
are connected to ground (0) through a programmable
fuse, selecting the “0” path through the multiplexer. Pro-
gramming the fuse disconnects the control line from
GND and it is driven to a high level, selecting the “1”
path.
The device is produced with a fuse link at each input to
the AND gate array, and connections may be selectively
removed by applying appropriate voltages to the circuit.
Variable Input/Output Pin Ratio
The PAL22V10 has twelve dedicated input lines, and
each macrocell output can be an I/O pin. Buffers for de-
vice inputs have complementary outputs to provide
user-programmable input signal polarity. Unused input
pins should be tied to V
CC
or GND.
CLK
S
1
1
1
0
0
0
1
0
1
AR
SP
0
1
I/O
n
S
0
S
1
0
0
1
1
S
0
0
1
0
1
Output Configuration
Registered/Active Low
Registered/Active High
Combinatorial/Active Low
Combinatorial/Active High
0 = Unprogrammed fuse
1 = Programmed fuse
16559C-4
D Q
Q
Figure 1. Output Logic Macrocell Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AMPAL22V10-10DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| AMPAL22V10-10DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| AMPAL22V10-10DE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| AMPAL22V10-10JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| AMPAL22V10-10LC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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