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參數(shù)資料
| 型號： | AMIS-52150 |
| 英文描述： | Low-Power Transceiver with Clock and Data Recovery |
| 中文描述： | 低功耗收發(fā)器時鐘和數(shù)據(jù)恢復(fù) |
| 文件頁數(shù)： | 9/25頁 |
| 文件大?。?/td> | 900K |
| 代理商： | AMIS-52150 |
AMIS-52150
Low-Power Transceiver with Clock and Data Recovery
Data Sheet
8.6 GND, Ground Pin
The GND pin is the ground connection for the digital and analog circuits.
8.7 CLKOUT, Internal Clock Output Pin
The CLKOUT pin is an output for the RC oscillator, crystal oscillator signal or the recovered data clock, respectively. The crystal
oscillator signal output can be divided by 2, 3 or 4. The pin can also be programmed to output the signal from the recovered data clock
function. For more information about the clock and data recovery (CDR) function of the AMIS-52150, refer to the section of this
document on clock and data recovery.
The CLKOUT pin function control registers are shown in Table 13.
Table 13: Oscillator Output Control Registers
CLKOUT Pin Definition Control Registers
Register (HEX)
Name
Bits
States
Comments
0x0c
CLKOUT enable
7
0
CLKOUT is enabled
1
CLKOUT is disabled
0x0d
CLKOUT select
4,5
00
Automatic control
01
RC OSC
10
Xtal
11
Off
0x0e
XTAL divide
0,1
00
Divide by 4
01
Divide by 3
10
Divide by 2
11
Divide by 1
8.8 X1, X2, External Crystal Reference Pins
X1 and X2 pins connect a parallel resonance oscillator crystal to the AMIS-52150 internal oscillator circuit. The external crystal should
meet the requirements as listed in Table 14. However, the two load capacitors should be sized slightly smaller than the recommended
value for the crystal, because of the added capacitance due to the internal trim circuit. For further details, refer to the application note
titled “Quick Start Crystal Oscillator Circuit Operation and Set-up”. The crystal parameters are shown in Table 14.
Table 14: External Crystal Parameters
Parameter
Min.
Typ.
Max.
Units
Conditions
Crystal frequency
12.56
12.65
MHz
Targeted
9.375
24.0
Non-Quick Start
10.9
14.0
Quick Start
Crystal ESR
70
Crystal tolerance
10
ppm
Load capacitance
Load capacitors should be smaller than recommended for
the crystal to allow for frequency tuning
8.9 I
2
CDATA, I
2
CCLK, I
2
C Control Interface Bus Pins
The AMIS-52150 implements an I
2
C serial 8-bit bi-directional interface with the pins I
2
CDATA and I
2
CCLK. The device implements the
protocol for a slave device. The clock for the interface is generated by the external master device. The interface will support the normal
(0 – 100 Kbits/second) or the fast (0 – 400Kbits/second) data modes. The interface conforms to the Phillips specification for the I
C bus
standard. The pins have internal pull-up resistors. See Table 15 and Table 16 for some parameters of this interface.
In addition, Table 17 shows the details of register that controls the I
2
C address increment function.
9
AMI Semiconductor
– Apr. 07 – M-20535-006
www.amis.com
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