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參數(shù)資料
| 型號： | AMIS-52150 |
| 英文描述： | Low-Power Transceiver with Clock and Data Recovery |
| 中文描述： | 低功耗收發(fā)器時鐘和數(shù)據(jù)恢復(fù) |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 900K |
| 代理商： | AMIS-52150 |
AMIS-52150
Low-Power Transceiver with Clock and Data Recovery
Data Sheet
recovery (see the application note titled “AMIS-52150 Clock and Data Recovery Circuit Operation and Set-Up”), the register shown in
Table 28 can be used to define the test mode operation.
Table 28: Clock and Data Recovery Test Mode
Clock and Data Recovery Test Control Register
Register (HEX)
Binary Code
HEX Code
Comments
0x1d
00001110
0x0e
Normal RSSI digital input
00001111
0x0f
CDR start bit digital input to RSSI
9.7 Wake-Up Function
Ultra-low power applications can take advantage of the wake-up function of the AMIS-52150. The AMIS-52150 can be placed in a low
power or “sleep” state until an interrupt based on the programmable wake-up timer is generated. This wakes up the transceiver, which
then flags the external microcontroller to perform the required application-specific operations. The wake-up interrupt is also generated
based on detection of RF energy (Sniff Mode
). Communication with the microcontroller takes place via the I
C bus. In addition, when
the AMIS-52150 is in the “sleep’” state, the wake-up signal can be generated by the microcontroller. Table 29 lists the registers
associated with the wake-up function.
Table 29: Application Wake-Up Control Registers
Application Wakeup Control Registers
Register (HEX)
Bits
States
Comments
0x14
AW TIMER DIV
All
Divides the RC oscillator to form a clock for the AW
0x15
AW TIMER
All
Number of AW clock periods before a AW wakeup
0x17
PRE/POST AW
DELAY
goes low for a AW cycle
All
Number of CLKOUT clock periods before the TX/RX pin
9.8 I
2
C Interface
The I
2
C is a two pin bi-directional serial interface communication bus, with a data line and a clock line, respectively. Serial data on the
data pin is clocked into or out of the AMIS-52150 by the clock pin. The AMIS-52150 is implemented as a slave device, which means
that the external controller is the master device. The clock signal for all transmissions between the master (controller) and the slave
(AMIS-52150) is generated by the controller. The serial communication bit rate can be as high as 400Kbps. A communication link is
initiated based on a start sequence. Bi-directional communication continues as long as the master and slave acknowledge the write or
read sequences, and is terminated with a stop sequence. This is illustrated in Figure 15, Figure 16 and Figure 17, respectively.
21
AMI Semiconductor
– Apr. 07 – M-20535-006
www.amis.com
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