參數(shù)資料
型號(hào)： AMIS-52100-M
英文描述： Transceiver with Clock and Data Recovery
中文描述： 收發(fā)器時(shí)鐘和數(shù)據(jù)恢復(fù)
文件頁數(shù)： 6/26頁
文件大小： 1040K
代理商： AMIS-52100-M
AMIS-52100
Low-Power Transceiver with Clock and Data Recovery
Data Sheet
Table 9: Package Dimensions: 209mil SSOP
Dm
Min.
A
0.068
A1
0.002
A2
0.065
b
0.009
D
0.271
E
0.291
E1
0.197
e
0.026 BSC
Inches
Millimeters
Max.
0.078
.20
0.073
0.015
0.295
0.323
0.221
Min.
1.73
0.05
1.65`
0.22
6.90
7.40
5.00
0.65 BSC
Max.
2.00
1.85
0.38
7.5
0.820
0.560
8.0 Pin Descriptions
8.1 RX1, RX2, RF Inputs
RX1 and RX2 are RF antenna inputs to the AMIS-52100. The internal circuit designs are identical between these inputs. The AMIS-
52100 receiver inputs, RX1 and RX2, require external components to match the low noise amplifier (LNA) to external devices such as
antennas. The external components must provide a DC voltage path to the RF ground. Figure 3 suggests an external circuit for the
receiver inputs at 403MHz. Each circuit’s input impedance can be trimmed internally to compensate for device manufacture and
external component tolerances. The circuits employ an LNA, internal filters, a low frequency, intermediate frequency (IF), and an
received signal strength indication (RSSI) circuit to recover the ASK/OOK modulated data. The signals in the two input channels are
“summed” before the data recovery circuit.
The functions of the receive circuits are controlled by writing to the registers shown in Table 10.
Table 10: Receiver Control Register Description
RX1 or RX2 Receiver Register Control
Register (HEX)
Name
Bits
States
Comments
0x00
ANT1 Trim
All
Inverse relationship register value to internal capacitance
0x01
ANT2 Trim
All
Inverse relationship register value to internal capacitance
0
Antenna port is off
ANT1 Enable
0
1
Antenna port is on
0
Antenna port is off
ANT2 Enable
1
1
Antenna port is on
0x0c
Figure 3: Typical Input Impedance Match to 50
(402MHz)
6
AMI Semiconductor
– Rev 4.0, Mar. 06 – M-20535-004
www.amis.com
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