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參數(shù)資料
| 型號(hào)： | AMIS-52100-M |
| 英文描述： | Transceiver with Clock and Data Recovery |
| 中文描述： | 收發(fā)器時(shí)鐘和數(shù)據(jù)恢復(fù) |
| 文件頁數(shù)： | 21/26頁 |
| 文件大?。?/td> | 1040K |
| 代理商： | AMIS-52100-M |
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AMIS-52100
Low-Power Transceiver with Clock and Data Recovery
Data Sheet
Table 27: Data and Clock Recovery Control Registers
Data and Clock Recovery Associated Registers
Register (HEX)
Name
0x07
FWORD LSB
0x08
FWORD
0x09
FWORD MSB
DATA MUX
0x0d
Bits
All
All
All
6
States
0
1
0
1
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
00
01
10
11
00
01
10
11
0
1
0
1
0
1
00
00
Comments
Sets the initial internal clock frequency for the clock and data
recovery circuits
TX/RX normal signals
Recovered data on TX/RX
Normal CLKOUT signals
Recovered CLOCK output on CLKOUT
Filter coefficient gain is 1
Filter coefficient gain is 2
Filter coefficient gain is 4
Filter coefficient gain is 8
Filter coefficient gain is 16
Filter coefficient gain is 32
Filter coefficient gain is 64
Filter coefficient gain is 128
Filter coefficient gain is 1
Filter coefficient gain is 2
Filter coefficient gain is 4
Filter coefficient gain is 8
Filter coefficient gain is 16
Filter coefficient gain is 32
Filter coefficient gain is 64
Filter coefficient gain is 128
Filter coefficient gain is 0.125
Filter coefficient gain is 0.250
Filter coefficient gain is 0.500
Filter coefficient gain is 1.000
Filter coefficient gain is 2
Filter coefficient gain is 4
Filter coefficient gain is 8
Filter coefficient gain is 16
Sample frequency divider is 2
Sample frequency divider is 4
Sample frequency divider is 8
Sample frequency divider is 16
Sample frequency divider is 20
Sample frequency divider is 32
Sample frequency divider is 40
Sample frequency divider is 48
StopCheck bits: disabled
StopCheck bits: 2
StopCheck bits: 4
StopCheck bits: 8
Loop clamp value is: +-BaudClk/8
Loop clamp value is: +-BaudClk/16
Loop clamp value is: +-BaudClk/32
Loop clamp value is: +-BaudClk/64
Phase alignment enabled
Phase alignment disabled
CDR reset disabled
CDR reset enabled
POR reset (auto)
CDR reset enabled (manual)
Sampling starts with bit start edge
Sampling centered around bit center
CLKMUX
7
K
0
0,1,2
0x10
K
1
4,5,6
K
2
0,1,2
0x11
FsDIV
4,5,6
STOP CHECK
0,1
LOOPCLAMP
2,3
FREERUN
4
CRD RESET
5
AUTO/MANUAL
RESET
SAMPLE
WINDOW
6
0x12
7
The clock and data recovery function requires that the receiver be able to recover the data from the incoming RF signal. There is a
method to test the clock and data recovery function without having to set the receiver up to receive data. This is a test mode that allows
an input data stream (square wave at
1
/
2
the data rate) to be input on the RSSI pin and recovered clock will appear on the CLKOUT pin
21
AMI Semiconductor
– Rev 4.0, Mar. 06 – M-20535-004
www.amis.com
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