參數(shù)資料
型號(hào)： AMIS-52100-M
英文描述： Transceiver with Clock and Data Recovery
中文描述： 收發(fā)器時(shí)鐘和數(shù)據(jù)恢復(fù)
文件頁(yè)數(shù)： 22/26頁(yè)
文件大?。?/td> 1040K
代理商： AMIS-52100-M
AMIS-52100
Low-Power Transceiver with Clock and Data Recovery
Data Sheet
while recovered data will appear on the TX/RX pin. The AMIS-52100 must be set up for clock and data recovery (See the AMIS
application note “Clock and Data Recovery Circuit Operation and Setup”). Then the following register in Table 28 defines the test select.
Table 28: Clock and Data Recovery Test Mode
Clock and Data Recovery Test Control Register
Register (HEX)
Binary Code
HEX Code
Comments
0x1d
00001110
0x0e
Normal RSSI digital input
00001111
0x0f
CDR start bit digital input to RSSI
9.7 Application Wakeup
Very low power applications can take advantage of the application wakeup function in the AMIS-52100. The AMIS-52100 is placed in a
low power or “sleep” state until the programmable application wakeup timer goes off. This wakes the AMIS-52100 so that it can alert the
external controller that the application may perform required operations. Since the AMIS-52100 can be awakened by either RF energy
detection, in Sniff Mode, or by the application wakeup timer, an external controller can interrogate the I
C bus pins to determine which
function cause the AMIS-52100 to wake. Also, when the AMIS-52100 is in the power down or “sleep’ state, an external controller can
wake it. Table 29 presents the registers associated with this application wakeup function.
Table 29: Application Wakeup Control Registers
Application Wakeup Control Registers
Register (HEX)
Name
Bits
States
Comments
0x14
AW TIMER DIV
All
Divides the RC oscillator to form a clock for the AW
0x15
AW TIMER
All
Number of AW clock periods before a AW wakeup
0x17
PRE/POST AW
DELAY
goes low for a AW cycle
All
Number of CLKOUT clock periods before the TX/RX pin
9.8 I
2
C Interface
The I
2
C is a two pin bi-directional serial interface communication bus. There is a data line and a clock line. Serial data on the data pin is
clocked into or out of the AMIS-52100 by the clock pin. The AMIS-52100 is implemented as a slave device, which means that an
external controller is the master. The master forms the clock signal for all transactions between the master (external controller) and the
slave (AMIS-52100). The slave device acknowledges writes to it and the master acknowledges reads from the slave. The serial bit rate
can be as high as 400Kbps and is set by the clock of the master. A communication link is started with a start sequence. Communication
continues as long as the master and slave acknowledge each write or read. Communication is ended with a stop sequence. These are
illustrated by Figure 15, Figure 16 and Figure 17.
22
AMI Semiconductor
– Rev 4.0, Mar. 06 – M-20535-004
www.amis.com
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