List of Figures
xiii
20695H/0—March 1998
AMD-K6
Processor Data Sheet
Preliminary Information
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
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Figure 80.
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Figure 90.
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Figure 92.
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Figure 96.
Figure 97.
Figure 98.
Figure 99.
Figure 100. AMD-K6 Processor Pin-Side View . . . . . . . . . . . . . . . . . . . . . . 268
Figure 101. 321-Pin Staggered CPGA Package Specification . . . . . . . . . . 272
SMM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
TAP State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . 218
Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . 219
Clock Control State Transitions . . . . . . . . . . . . . . . . . . . . . . . . 228
Suggested Component Placement . . . . . . . . . . . . . . . . . . . . . . 230
K6STD Pulldown V/I Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
K6STD Pullup V/I Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Diagrams Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Output Valid Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Maximum Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . .255
Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . 256
TCK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
TRST# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Test Signal Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Thermal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Power Consumption vs. Thermal Resistance . . . . . . . . . . . . . 260
Processor Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . 261
Measuring Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 262
Voltage Regulator Placement. . . . . . . . . . . . . . . . . . . . . . . . . . 263
Airflow for a Heatsink with Fan. . . . . . . . . . . . . . . . . . . . . . . . 263
Airflow Path in a Dual-fan System . . . . . . . . . . . . . . . . . . . . . . 264
Airflow Path in an ATX Form-Factor System . . . . . . . . . . . . . 265
AMD-K6 Processor Top-Side View . . . . . . . . . . . . . . . . . . . . . . 267
Part Two
AMD-K6 Processor Model 7
275
Figure 102. Extended Feature Enable Register (EFER) . . . . . . . . . . . . . .282
Figure 103. SYSCALL/SYSRET Target Address Register (STAR) . . . . . . 283
Figure 104. AMD-K6 Processor Model 7 Top-Side View. . . . . . . . . . . . . . . 315
Figure 105. AMD-K6 Processor Model 7 Pin-Side View . . . . . . . . . . . . . . . 316