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參數(shù)資料
| 型號： | AM85C30-8 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Enhanced Serial Communications Controller |
| 中文描述： | 增強的串行通信控制器 |
| 文件頁數(shù)： | 23/68頁 |
| 文件大?。?/td> | 553K |
| 代理商： | AM85C30-8 |
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AMD
23
Am85C30
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Write Register 12
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
TC
0
TC
1
TC
2
TC
3
TC
4
TC
5
TC
6
TC
7
Lower Byte of
Time Constant
Write Register 14
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
BR Generator Enable
BR Generator Source
DTR
/Request Function
Auto Echo
Local Loopback
Write Register 10
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
6-Bit/
8-Bit
Sync
Loop Mode
Abort/
Flag
on Underrun
Mark/
Flag
Idle
Go Active on Roll
0
0
1
1
0
1
0
1
NRZ
NRZI
FM1 (Transition = 1)
FM0 (Transition = 0)
CRC Preset ‘1’ or ‘0’
Write Register 13
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
TC
8
TC
9
TC
10
TC
11
TC
12
TC
13
TC
14
TC
15
Upper Byte of
Time Constant
Null Command
Enter Search Mode
Reset Missing Clock
Disable DPLL
Set Source = BR Generator
Set Source =
RTxC
Set FM Mode
Set NRZI Mode
Write Register 15
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SDLC/HDLC Enhancements Enable*
Zero Count IE
10
×
19 Bit FIFO Enable*
DCD IE
Sync/Hunt IE
CTS IE
Tx Underrun/EOM IE
Break/Abort IE
* Added Enhancement
Figure 9. Write Register Bit Functions (continued)
10216F-13
(concluded)
Am85C30 Timing
The ESCC generates internal control signals from
WR
and
RD
that are related to PCLK. Since PCLK has no
phase relationship with
WR
and
RD
, the circuitry gener-
ating these internal control signals must provide time for
metastable conditions to disappear. This gives rise to a
recovery time related to PCLK. The recovery time ap-
plies only between bus transactions involving the
ESCC. The recovery time required for proper operation
is specified from the falling edge of
WR
or
RD
in the first
transaction involving the ESCC, to the falling edge of
WR
or
RD
in the second transaction involving the
ESCC. This time must be at least 3 1/2 PCLK regardless
of which register or channel is being accessed.
Read Cycle Timing
Figure 10 illustrates Read cycle timing. Addresses on
A/
B
and D/
C
and the status on
INTACK
must remain sta-
ble throughout the cycle. If
CE
falls after
RD
falls or if it
rises before
RD
rises, the effective
RD
is shortened.
Write Cycle Timing
Figure 11 illustrates Write cycle timing. Addresses on
A/
B
and D/
C
and the status on
INTACK
must remain
stable throughout the cycle. If
CE
falls after
WR
falls or if
it rises before
WR
rises, the effective
WR
is shortened.
Data must be valid before the rising edge of
WR
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM85C30-8BQA | Enhanced Serial Communications Controller |
| AM8T-1203SC | 8 watt dc-dc converters |
| AM8T-1205DC | 8 watt dc-dc converters |
| AM8T-1205SC | 8 watt dc-dc converters |
| AM8T-1212DC | 8 watt dc-dc converters |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM85C30-8/BQA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM85C30-8/BUA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM85C30-8BQA | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Enhanced Serial Communications Controller |
| AM85C30-8BUA | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Enhanced Serial Communications Controller |
| AM85C308JC | 制造商:AMD 功能描述:* |
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