參數(shù)資料
型號(hào)： AM85C30-8
廠商： Advanced Micro Devices, Inc.
英文描述： Enhanced Serial Communications Controller
中文描述： 增強(qiáng)的串行通信控制器
文件頁(yè)數(shù)： 13/68頁(yè)
文件大小： 553K
代理商： AM85C30-8
AMD
13
Am85C30
Sync
Data
Data
Sync
Sync
Data
Data
5 Bits
8 Bits
16 Bits
Figure 4. Detecting 5- or 7-Bit Synchronous Characters
10216F-8
with no need for CPU intervention at the end of a mes-
sage. When there are no data or CRC to send in SYNC
modes, the transmitter inserts 6-, 8-, or 16-bit SYNC
characters, regardless of the programmed character
length.
The ESCC supports SYNC bit-oriented protocols, such
as SDLC and HDLC, by performing automatic flag send-
ing, zero-bit insertion, and CRC generation. A special
command can be used to abort a frame in transmission.
At the end of a message, the ESCC automatically trans-
mits the CRC and trailing flag when the transmitter un-
derruns. The transmitter may also be programmed to
send an idle line consisting of continuous flag charac-
ters or a steady marking condition.
If a transmit underrun occurs in the middle of a mes-
sage, an external/status interrupt warns the CPU of this
status change so that an abort may be issued. The
ESCC may also be programmed to send an abort itself
in case of an underrun, relieving the CPU of this task.
One to 8 bits per character can be sent allowing recep-
tion of a message with no prior information about the
character structure in the information field of a frame.
The receiver automatically acquires synchronization on
the leading flag of a frame in SDLC or HDLC and pro-
vides a synchronization signal on the
SYNC
pin (an in-
terrupt can also be programmed). The receiver can be
programmed to search for frames addressed by a single
byte (or 4 bits within a byte) of a user-selected address
or to a global broadcast address. In this mode, frames
not matching either the user-selected or broadcast ad-
dress are ignored. The number of address bytes can be
extended under software control. For receiving data, an
interrupt on the first received character, or an interrupt
on every character, or on special condition only (end-of-
frame) can be selected. The receiver automatically de-
letes all 0s inserted by the transmitter during character
assembly. CRC is also calculated and is automatically
checked to validate frame transmission. At the end of
transmission, the status of a received frame is available
in the status registers. In SDLC mode, the ESCC must
be programmed to use the SDLC CRC polynomial,
but the generator and checker may be preset to all 1s
or all 0s. The CRC is inverted before transmission
and the receiver checks against the bit pattern
0001110100001111.
NRZ, NRZI or FM coding may be used in any 1X mode.
The parity options available in asynchronous modes are
available in synchronous modes.
The ESCC can be conveniently used under DMA control
to provide high-speed reception or transmission. In re-
ception, for example, the ESCC can interrupt the CPU
when the first character of a message is received. The
CPU then enables the DMA to transfer the message to
memory. The ESCC then issues an end-of-frame inter-
rupt and the CPU can check the status of the received
message. Thus, the CPU is freed for other service while
the message is being received. The CPU may also en-
able the DMA first and have the ESCC interrupt only on
end-of-frame. This procedure allows all data to be trans-
ferred via the DMA.
SDLC Loop Mode
The ESCC supports SDLC Loop mode in addition to
normal SDLC. In a SDLC Loop, there is a primary con-
troller station that manages the message traffic flow and
any number of secondary stations. In SDLC Loop mode,
the ESCC performs the functions of a secondary station
while an ESCC operating in regular SDLC mode can act
as a controller (Figure 5).
Controller
Secondary #1
Secondary #2
Secondary #3
Secondary #4
Figure 5. A SDLC Loop
10216F-9
A secondary station in a SDLC Loop is always listening
to the messages being sent around the loop and, in fact,
must pass these messages to the rest of the loop by
retransmitting them with a 1-bit time delay. The sec-
ondary station can place its own message on the loop
only at specific times. The controller signals that secon-
dary stations may transmit messages by sending a spe-
cial character, called an EOP (End of Poll), around the
loop. The EOP character is the bit pattern 11111110.
Because of zero insertion during messages, this bit pat-
tern is unique and easily recognized.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM85C30-8/BQA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller
AM85C30-8/BUA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller
AM85C30-8BQA 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Enhanced Serial Communications Controller
AM85C30-8BUA 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Enhanced Serial Communications Controller
AM85C308JC 制造商:AMD 功能描述:*
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