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Am79C971
107
I
PCI Configuration Registers
These registers are intended to be initialized by the
system initialization procedure (e.g., BIOS device ini-
tialization routine) to program the operation of the
Am79C971 controller PCI bus interface.
The following is a list of the registers that would typi-
cally need to be programmed once during the initializa-
tion of the Am79C971 controller within a system:
—
PCI I/O Base Address or Memory Mapped I/O
Base Address register
—
PCI Expansion ROM Base Address register
—
PCI Interrupt Line register
—
PCI Latency Timer register
—
PCI Status register
—
PCI Command register
I
Setup Registers
These registers are intended to be initialized by the de-
vice driver to program the operation of various
Am79C971 controller features.
The following is a list of the registers that would typi-
cally need to be programmed once during the setup of
the Am79C971 controller within a system. The control
bits in each of these registers typically do not need to
be modified once they have been written. However,
there are no restrictions as to how many times these
registers may actually be accessed. Note that if the de-
fault power up values of any of these registers is ac-
ceptable to the application, then such registers need
never be accessed at all.
Note:
Registers marked with
“
^
”
may be programma-
ble through the EEPROM read operation and, there-
fore, do not necessarily need to be written to by the
system initialization procedure or by the driver soft-
ware. Registers marked with
“
*
”
will be initialized by the
initialization block read operation.
CSR1
Initialization Block Address[15:0]
CSR2*
Initialization Block Address[31:16]
CSR3
Interrupt Masks and Deferral Control
CSR4
Test and Features Control
CSR5
Extended Control and Interrupt
CSR7
Extended Control and Interrupt2
CSR8*
Logical Address Filter[15:0]
CSR9*
Logical Address Filter[31:16]
CSR10*
Logical Address Filter[47:32]
CSR11*
Logical Address Filter[63:48]
CSR12*^
Physical Address[15:0]
CSR13*^
Physical Address[31:16]
CSR14*^
Physical Address[47:32]
CSR15*
Mode
CSR24*
Base Address of Receive Ring Lower
CSR25*
Base Address of Receive Ring Upper
CSR30*
Base Address of Transmit Ring Lower
CSR31*
Base Address of Transmit Ring Upper
CSR47*
Transmit Polling Interval
CSR49*
Receive Polling Interval
CSR76*
Receive Ring Length
CSR78*
Transmit Ring Length
CSR80
DMA
Threshold Control
Transfer
Counter
and
FIFO
CSR82
Bus Activity Timer
CSR100
Memory Error Timeout
CSR122
Receiver Packet Alignment Control
CSR125^
MAC Enhanced Configuration Control
BCR2^
Miscellaneous Configuration
BCR4^
LED0 Status
BCR5^
LED1 Status
BCR6^
LED2 Status
BCR7^
LED3 Status
BCR9^
Full-Duplex Control
BCR18^
Bus and Burst Control
BCR19
EEPROM Control and Status
BCR20
Software Style
BCR22^
PCI Latency
BCR23^
PCI Subsystem Vendor ID
BCR24^
PCI Subsystem ID
BCR25^
SRAM Size
BCR26^
SRAM Boundary
BCR27^
SRAM Interface Control
BCR32^
MII Control and Status
BCR33^
MII Address
BCR35^
PCI Vendor ID
I
Running Registers
These registers are intended to be used by the device
driver software after the Am79C971 controller is running
to access status information and to pass control infor-
mation.