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參數(shù)資料
| 型號： | AM79C875KC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | NetPHY⑩ 4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 20 MM, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 33/48頁 |
| 文件大?。?/td> | 2480K |
| 代理商： | AM79C875KC |
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Am79C875
33
Receive Error Counter (Register 21)
Table 21. Receive Error Counter (Register 21)
Reg
21
Bit
15:0
Name
Description
Count of Receive Error Events.
Read/
Write
RW
Default
0000 (hex)
RX_ER Counter
Mode Control Register (Register 24)
Table 22. Mode Control Register (Register 24)
Reg
Bit
Name
Description
Read/
Write
Default
24
15
SDCM_SEL
Select Common Mode Voltage Setting for FX Signal Detect (SDI)
input signal.
1 = Select Internal Common Mode Setting.
0 = Select External Common Voltage Setting.
RW
0
24
14
Force 10BASE-T
Link Up
1 = Force link up at 10 Mbps without checking NLP. Auto-
Negotiation must be disabled and the data rate must be 10 Mbps.
0 = Normal Operation.
RW
0
24
13
Force
100BASE-TX
Link Up
1 = Force link up at 100 Mbps. Auto-Negotiation must be disabled
and the data rate must be 100 Mbps.
0 = Normal Operation.
RW
0
24
12
Jabber Disable
1 = Disable Jabber function in PHY.
0 = Enable Jabber function in PHY.
RW
0
24
11
Reserved
Write as 0, ignore when read.
RW
0
24
10
Activity LED
Configuration
1 = Activity only responds to receive operation.
0 = Activity responds to Receive and transmit.
In repeater mode, this bit will be ignored.
RW
1
24
9
Reserved
Write as 0, ignore when read.
RW
0
24
8
FEFI_Disable
Set this bit will disable FEFI generation and detection function. The
default value of this bit is 0 when the chip is working in FX mode.
Otherwise the default value is 1.
RW
Set by
FX_DIS and
ANEGA pins
24
7
Force FEFI
Transmit
This bit is set to force the transmit FEFI pattern.
RW
0
24
6
RX_ER_CNT Full
Disable
RX_ER counter
This bit is set to one to indicate the Receive Error Counter is full.
RO/RC
0
24
5
1 = disable Receive Error Counter.
RW
0
24
4
DIS_WDT
1 = Disable the watchdog timer in the decipher.
RW
0
24
3
EN_RPBK
1 = Enable remote loopback, 0 = Disable remote loopback.
RW
0
24
2
EN_SCRM
0 = Disable data scrambling.
1 = Enable data scrambling.
When FX_DIS pin is asserted low or FX_SEL bit (Register 24.0) is
set to logic high, this bit will be overwritten as “1” automatically.
The default of this bit is set by power on read value of FX_DIS.
RW
Set by
SCRAM_EN
pin
24
1
Reserved
Write as 0, ignore when read.
RO
0
24
0
FX_SEL
Set this bit to logic 1 to select 100BASE-FX mode, set to logic 0 to
select 100BASE-TX.
RW
Set by
FX_DIS
pin
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C875KD | 制造商:Advanced Micro Devices 功能描述:PHY 4-CH 10Mbps/100Mbps 100-Pin PQR 制造商:Advanced Micro Devices 功能描述:NPD IC OPN ETHERNET TRANSCEIVER 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 4-CH 10Mbps/100Mbps 100-Pin PQR |
| AM79C875KF | 制造商:Advanced Micro Devices 功能描述:PHY 4-CH 10Mbps/100Mbps 100-Pin PQR 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 4-CH 10Mbps/100Mbps 100-Pin PQR |
| AM79C875KI | 制造商:Advanced Micro Devices 功能描述:PHY 4-CH 10Mbps/100Mbps 100-Pin PQR 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 4-CH 10Mbps/100Mbps 100-Pin PQR |
| AM79C90 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:CMOS Local Area Network Controller for Ethernet (C-LANCE) |
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