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參數(shù)資料
| 型號： | Am70PDL127CDH66IS |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| 中文描述： | 2 × 64兆位（8米× 16位）的CMOS 3.0伏特，只有頁面模式閃存數(shù)據(jù)存儲128兆位（8米× 16位）的CMOS |
| 文件頁數(shù)： | 62/127頁 |
| 文件大小： | 849K |
| 代理商： | AM70PDL127CDH66IS |
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60
Am70PDL127CDH/Am70PDL129CDH
November 24, 2003
A D V A N C E I N F O R M A T I O N
DC CHARACTERISTICS
CMOS Compatible
Notes:
1.
Valid CE#f1/CE#f2 conditions (PDL129 only): (CE#f1= V
IL
, CE#f2=
V
IH
) or (CE#f1= V
IH
, CE#f2= V
IL
)
The I
CC
current listed is typically less than 5 mA/MHz, with OE# at
V
IH
.
Maximum I
CC
specifications are tested with V
CC
= V
CCmax
.
2.
3.
4.
I
active while Embedded Erase or Embedded Program is in
progress.
Automatic sleep mode enables the low power mode when
addresses remain stable for t
ACC
+ 150 ns. Typical sleep mode
current is 1
μ
A.
Not 100% tested.
5.
6.
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
I
LI
Input Load Current
V
IN
= V
SS
to V
CC
,
V
CC
= V
CC
max
±
1.0
μA
I
LIT
A9, OE#, RESET# Input Load Current
V
CC
= V
CC max
; V
ID
= 12.5 V
35
μA
I
LR
Reset Leakage Current
V
CC
= V
CC max
; V
ID
= 12.5 V
V
OUT
= V
SS
to V
CC
, OE# = V
IH
V
CC
= V
CC max
35
μA
I
LO
Output Leakage Current
±
1.0
μA
I
CC1
V
CC
Active Read Current (Notes 1, 2, 3)
OE# = V
IH
, V
CC
= V
CC max
(Note 1)
5 MHz
20
30
mA
10 MHz
45
55
I
CC2
V
CC
Active Write Current (Notes 1, 3, 4)
OE# = V
IH
, WE# = V
IL
CE#f1, CE#f2 (PDL129 only),
RESET#, WP/ACC# = V
IO
±
0.3 V
RESET# = V
SS
±
0.3 V, CE# = V
SS
V
IH
= V
IO
±
0.3 V;
V
IL
= V
SS
±
0.3 V, CE# = V
SS
15
25
mA
I
CC3
V
CC
Standby Current (Note 3)
1
5
μA
I
CC4
V
CC
Reset Current (Note 3)
1
5
μA
I
CC5
Automatic Sleep Mode (Notes 3, 5)
1
5
μA
I
CC6
V
Active Read-While-Program Current
(Notes 1, 2, 3)
OE# = V
IH
Word
21
45
mA
I
CC7
V
Active Read-While-Erase Current
(Notes 1, 2, 3)
OE# = V
IH
Word
21
45
mA
I
CC8
V
Active Program-While-Erase-
Suspended Current (Notes 1, 3, 6)
OE# = V
IH
17
25
mA
V
IL
Input Low Voltage
V
IO
= 2.7–3.6 V
–0.5
0.8
V
V
IH
Input High Voltage
V
IO
= 2.7–3.6 V
2.0
V
CC
+0.3
V
V
HH
Voltage for ACC Program Acceleration
V
CC
= 3.0 V ± 10%
8.5
9.5
V
V
ID
Voltage for Autoselect and Temporary
Sector Unprotect
V
CC
= 3.0 V
±
10%
11.5
12.5
V
V
OL
Output Low Voltage
I
OL
= 2.0 mA, V
CC
= V
CC min
0.4
V
V
OH
Output High Voltage
I
OH
= –2.0 mA, V
CC
= V
CC min
2.4
V
V
LKO
Low V
CC
Lock-Out Voltage (Note 6)
2.3
2.5
V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Am70PDL127CDH66IT | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| Am70PDL127CDH85IS | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| Am70PDL127CDH85IT | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| Am70PDL129CDH | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| Am70PDL129CDH66IS | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM70PDL127CDH66IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH85I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH85IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH85IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL129BDH | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
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