參數(shù)資料
型號: AM53CF96KC
廠商: ADVANCED MICRO DEVICES INC
元件分類: 總線控制器
英文描述: Enhanced SCSI-2 Controller (ESC)
中文描述: SCSI BUS CONTROLLER, PQFP100
封裝: METRIC, PLASTIC, QFP-100
文件頁數(shù): 27/76頁
文件大?。?/td> 735K
代理商: AM53CF96KC
P R E L I M I N A R Y
AMD
27
Am53CF94/Am53CF96
Synchronous Transfer Period Register (06H) Write
6
Synchronous Transfer Period Register
STPREG
7
Address: 06
H
Type: Write
0
5
4
3
2
1
RES
RES
RES
STP4
STP3
STP2
STP1
STP0
x
x
x
0
0
1
0
1
Reserved
Reserved
Reserved
Synchronous Transfer Period 4:0
17348B-25
The Synchronous Transfer Period Register (STPREG)
contains a 5-bit value indicating the number of clock cy-
cles each byte will take to be transferred over the SCSI
bus in synchronous mode. The minimum value allowed
is 4. The STPREG defaults to 5 clocks/byte after a hard
or soft reset.
STPREG – Bits 7:5 – RES – Reserved
STPREG – Bits 4:0 – STP 4:0 – Synchronous
Transfer Period 4:0
The STP 4:0 bits are programmed to specify the syn-
chronous transfer period or the number of clock cycles
for each byte transfer in the synchronous mode. The
minimum value for STP 4:0 is 4 clocks/byte. Missing
table entries follow the binary code.
Clocks/
Byte
4
5
6
7
31
32
33
34
35
STP4
0
0
0
0
1
0
0
0
0
STP3
0
0
0
0
1
0
0
0
0
STP2
1
1
1
1
1
0
0
0
0
STP1
0
0
1
1
1
0
0
1
1
STP0
0
1
0
1
1
0
1
0
1
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