參數(shù)資料
型號(hào)： AM53CF96KC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 總線控制器
英文描述： Enhanced SCSI-2 Controller (ESC)
中文描述： SCSI BUS CONTROLLER, PQFP100
封裝： METRIC, PLASTIC, QFP-100
文件頁(yè)數(shù)： 22/76頁(yè)
文件大?。?/td> 735K
代理商： AM53CF96KC
P R E L I M I N A R Y
AMD
22
Am53CF94/Am53CF96
Interrupt Status Register (05H) Read
SRST
ICMD
DIS
SR
SO
0
0
0
0
0
Interrupt Status Register
INSTREG
Address: 05h
Type: READ
7
6
5
4
3
2
1
0
RESEL
SELA
SEL
0
0
0
Invalid Command
SCSI Reset
Disconnected
Service Request
Successful Operation
Selected with Attention
Reselected
Selected
17348B-22
The Interrupt Status Register (INSTREG) will indicate
the reason for the interrupt. This register is used with the
Status Register (STATREG) and Internal State Register
(ISREG) to determine the reason for the interrupt.
Reading the INSTREG will clear all three registers.
Therefore the Status Register (STATREG) and Internal
State Register (ISREG) should be examined prior to
reading the INSTREG.
INSTREG – Bit 7 – SRST – SCSI Reset
The SRST bit will be set if a SCSI Reset is detected and
SCSI reset reporting is enabled via the DISR (bit 6) of
Control Register One (CNTLREG1).
INSTREG – Bit 6 – ICMD – Invalid Command
The ICMD bit will be set if the device detects an illegal
command code. This bit is also set if a command code is
detected from a mode that is different from the mode the
device is currently in. Once this bit is set, and invalid
command interrupt will be generated.
INSTREG – Bit 5 – DIS – Disconnected
The DIS bit can be set in the Target or the Initiator mode
when the device disconnects from the SCSI bus. In the
Target mode this bit will be set if a Terminate or a Com-
mand Complete steps causes the device to disconnect
from the SCSI bus. In the Initiator mode this bit will be
set if the Target disconnects; while in Idle mode, this bit
will be set if a selection or reselection timeout occurs.
INSTREG – Bit 4 – SR – Service Request
The SR bit can be set in the Target or the Initiator mode
when another device on the SCSI bus has a service
request. In the Target mode this bit will be set when the
Initiator asserts the
ATN
signal. In the Initiator mode this
bit is set when a Command Steps Successfully Com-
pleted Command is issued.
INSTREG – Bit 3 – SO – Successful Operation
The SO bit can be set in the Target or the Initiator mode
when an operation has successfully completed. In the
Target mode this bit will be set when any Target or Idle
state command is completed. In the Initiator mode this
bit is set after a Target has been successfully selected,
after a command has successfully completed and after
an information transfer command when the Target
requests a Message In phase.
INSTREG – Bit 2 – RESEL – Reselected
The RESEL bit is set at the end of the reselection phase
indicating that the device has been reselected as an
Initiator.
INSTREG – Bit 1 – SELA – Selected with Attention
The SELA bit is set at the end of the selection phase indi-
cating that the device has been selected as a Target by
the Initiator and that the
ATN
signal was active during
the selection.
INSTREG – Bit 0 – SEL – Selected
The SEL bit is set at the end of the selection phase indi-
cating that the device has been selected as a Target by
the Initiator and that the
ATN
signal was inactive during
the selection.
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