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參數(shù)資料
| 型號(hào)： | AM53CF96KC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 總線控制器 |
| 英文描述： | Enhanced SCSI-2 Controller (ESC) |
| 中文描述： | SCSI BUS CONTROLLER, PQFP100 |
| 封裝： | METRIC, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 20/76頁 |
| 文件大?。?/td> | 735K |
| 代理商： | AM53CF96KC |
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P R E L I M I N A R Y
AMD
20
Am53CF94/Am53CF96
Status Register (04H) Read
Status Register
STATREG
Address: 04
H
Type: Read
7
6
5
4
3
2
1
0
INT
IOE
PE
CTZ
GCV
MSG
C/D
I/O
0
0
0
0
0
x
x
x
Illegal Operation Error
Interrupt
Parity Error
Count to Zero
Group Code Valid
Message
Command/Data
Input/Output
17348B-20
This read only register contains flags to indicate the
status and phase of the SCSI transactions. It indicates
whether an interrupt or error condition exists. It should
be read every time the host is interrupted to determine
which device is asserting an interrupt. If the ENF bit is
set (CNTLREG2, bit 6), the SCSI bus phase of the last
complete command (preceding the interrupt) will be
latched until the Interrupt Status Register (INSTREG) is
read. If the ENF bit is disabled, this register will reflect
the current bus phase. If command stacking is used, two
interrupts might occur. Reading this register will clear
the status information for the first interrupt and update
the Status Register for the second interrupt.
STATREG – Bit 7 – INT – Interrupt
The INT bit is set when the device asserts the interrupt
output. This bit will be cleared by a hardware or software
reset. Reading the Interrupt Status Register (INSTREG)
will deassert the interrupt output and also clear this bit.
STATREG – Bit 6 – IOE – Illegal Operation Error
The IOE bit is set when an illegal operation is attempted.
This condition will not cause an interrupt, it will be de-
tected by reading the Status Register (STATREG) while
servicing another interrupt. The following conditions will
cause the IOE bit to be set:
DMA and SCSI transfer directions are opposite.
I
FIFO overflows or data is overwritten.
I
In Initiator mode an unexpected phase change
detected during synchronous data transfer.
I
Command Register overwritten.
This bit will be cleared by reading the Interrupt Status
Register (INSTREG) or by a hard or soft reset.
I
STATREG – Bit 5 – PE – Parity Error
The PE bit is set if any of the parity checking options are
enabled and the device detects a parity error on bytes
sent or received on the SCSI Bus. Parity options are
controlled by bits 5:4 in Control Register One
(CNTLREG1), and by bits 2:0 in Control Register Two
(CNTLREG2). The combination of enabled options will
determine if parity is generated from the data bytes
internally by the chip, or if it is passed between buffer
and SCSI Bus without being altered. Detection of a
parity error condition will not cause an interrupt but will
be reported with other interrupt causing conditions.
This bit will be cleared by reading the Interrupt Status
Register (INSTREG) or by a hard or soft reset.
STATREG – Bit 4 – CTZ – Count To Zero
The CTZ bit is set when the Current Transfer Count
Register (CTCREG) has counted down to zero. This bit
will be reset when the CTCREG is written with a non-
zero value.
Reading the Interrupt Status Register (INSTREG) will
not affect this bit. This bit will however be cleared by a
hard or soft reset.
Note:
A non-DMA NOP will not reset the CTZ bit since it does
not load the CTCREG. However, a DMA NOP will reset
this bit since it loads the CTCREG.
STATREG – Bit 3 – GCV – Group Code Valid
The GCV bit is set if the group code field in the Com-
mand Descriptor Block (CDB) is one that is defined by
the ANSI Committee in their document X3.131 – 1986. If
the SCSI-2 Feature Enable (S2FE) bit in the Control
Register 2 (CNTLREG2) is set, Group 2 commands will
be treated as ten byte commands and the GCV bit will be
set. If S2FE is reset then Group 2 commands will be
treated as reserved commands. Group 3 and 4 com-
mands will always be considered reserved commands.
The device will treat all reserved commands as six byte
commands. Group 6 commands will always be treated
as vendor unique six byte commands and Group 7 com-
mands will always be treated as vendor unique ten byte
commands.
The GCV bit is cleared by reading the Interrupt Status
Register (INSTREG) or by a hard or soft reset.
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