參數(shù)資料
型號: AM50DLI28BG
廠商: Advanced Micro Devices, Inc.
元件分類: SRAM
英文描述: Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述: 堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 9/64頁
文件大?。?/td> 974K
代理商: AM50DLI28BG
8
Am50DL128BG
January 8, 2003
P R E L I M I N A R Y
PIN DESCRIPTION
A20–A0
= 21 Address Inputs (Common)
A21, A-1
= 2 Address Inputs (Flash)
DQ15–DQ0
= 16 Data Inputs/Outputs (Common)
CE#f1
= Chip Enable 1 (Flash 1)
CE#f2
= Chip Enable 2 (Flash 2)
CE#1s
= Chip Enable 1 (pSRAM)
CE2s
= Chip Enable 2 (pSRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output
UB#s
= Upper Byte Control (pSRAM)
LB#s
= Lower Byte Control (pSRAM)
CIOf
= I/O Configuration (Flash)
CIOf = V
IH
= Word mode (x16),
CIOf = V
IL
= Byte mode (x8)
= Hardware Reset Pin, Active Low
RESET#
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
V
CC
f
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
V
CC
s
V
SS
NC
= pSRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
LOGIC SYMBOL
21
16 or 8
DQ15–DQ0
A20–A0
CE#f1
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
SA
A21, A-1
LB#s
CIOf
CE#1s
CE2s
CE#f2
相關(guān)PDF資料
PDF描述
Am50DL128BG70I Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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