參數(shù)資料
型號： AM50DLI28BG
廠商： Advanced Micro Devices, Inc.
元件分類： SRAM
英文描述： Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述： 堆疊式多芯片封裝（MCP）閃存和SRAM
文件頁數(shù)： 12/64頁
文件大?。?/td> 974K
代理商： AM50DLI28BG
January 8, 2003
Am50DL128BG
11
P R E L I M I N A R Y
Table 1.
Device Bus Operations—Flash Word Mode, CIOf = V
IH
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5–12.5
V, V
HH
= 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, A
IN
=
Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1.
Other operations except for those indicated in this column are
inhibited.
Do not apply CE#f1 or 2 = V
IL
, CE1#s = V
IL
and CE2s = V
IH
at the
same time.
2.
3.
Active flash is device being addressed.
4.
Don’t care or open LB#s or UB#s.
5.
If WP#/ACC = V
, the boot sectors will be protected. If WP#/ACC
= V
the boot sectors protection will be removed.
If WP#/ACC = V
ACC
(9V), the program time will be reduced by
40%.
6.
The sector protect and sector unprotect functions may also be
implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
7.
If WP#/ACC = V
, the two outermost boot sectors remain
protected. If WP#/ACC = V
, the two outermost boot sector
protection depends on whether they were last protected or
unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP#/ACC = V
HH,
all sectors will
be unprotected.
8.
Data will be retained in pSRAM.
9.
Data will be lost in pSRAM.
10. CE# inputs on both flash devices may be held low for this operation.
Operation
(Notes 1, 2)
CE#f
Active
CE#f
Inactive
CE1#s
CE2s
OE#
WE#
Addr.
LB#s
(Note
4)
UB#s
(Note
4)
RESET#
WP#/
ACC
(Note 5)
DQ7–
DQ0
DQ15–
DQ8
(Note 3)
Read from
Active Flash
(Note 8)
L
H
H
H
L
H
A
IN
X
X
H
L/H
D
OUT
D
OUT
(Note 9)
H
L
Write to Active
Flash
(Note 8)
L
H
H
H
H
L
A
IN
X
X
H
(Note 5)
D
IN
D
IN
(Note 9)
H
L
Standby
V
CC
±
0.3 V
H
H
X
X
X
X
X
V
CC
±
0.3 V
H
High-Z
High-Z
Deep Power-down
Standby
V
CC
±
0.3 V
H
L
X
X
X
X
X
V
CC
±
0.3 V
H
High-Z
High-Z
Output Disable (Note 10)
L
H
L
H
H
H
X
X
X
H
L/H
High-Z
High-Z
H
H
X
X
X
Flash Hardware
Reset
(Note 8)
X
H
H
X
X
X
X
X
L
L/H
High-Z
High-Z
(Note 9)
H
L
Sector Protect
(Notes 6, 10)
(Note 8)
L
H
H
H
H
L
SADD,
A6 = L,
A1 = H,
A0 = L
X
X
V
ID
L/H
D
IN
X
(Note 9)
H
L
Sector
Unprotect
(Notes 6, 10)
(Note 8)
L
H
H
H
H
L
SADD,
A6 = H,
A1 = H,
A0 = L
X
X
V
ID
(Note 7)
D
IN
X
(Note 9)
H
L
Temporary
Sector
Unprotect
(Note 8)
X
H
H
X
X
X
X
X
V
ID
(Note 7)
D
IN
High-Z
(Note 9)
H
L
Read from pSRAM
H
H
L
H
L
H
A
IN
L
L
H
X
D
OUT
D
OUT
H
L
High-Z
D
OUT
L
H
D
OUT
High-Z
Write to pSRAM
H
H
L
H
X
L
A
IN
L
L
H
X
D
IN
D
IN
H
L
High-Z
D
IN
L
H
D
IN
High-Z
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