參數(shù)資料
型號(hào)： AM50DL128BH85I
廠商： Advanced Micro Devices, Inc.
元件分類： SRAM
英文描述： Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述： 堆疊式多芯片封裝（MCP）閃存和SRAM
文件頁(yè)數(shù)： 62/68頁(yè)
文件大?。?/td> 959K
代理商： AM50DL128BH85I
60
Am50DL128BH
October 7, 2003
A D V A N C E I N F O R M A T I O N
FLASH ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 3.0 V V
CC
, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90
°
C, V
CC
= 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
12 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Note:
Includes all pins except V
CC
. Test conditions: V
CC
= 3.0 V, one pin at a time.
PACKAGE PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.4
5
sec
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
56
sec
Byte Program Time
5
150
μs
Excludes system level
overhead (Note 5)
Accelerated Byte/Word Program Time
4
120
μs
Accelerated Chip Programming Time
10
30
sec
Word Program Time
7
210
μs
Chip Program Time
(Note 3)
Byte Mode
42
126
sec
Word Mode
28
84
Description
Min
Max
Input voltage with respect to V
SS
on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to V
SS
on all I/O pins
–1.0 V
V
CC
+ 1.0 V
V
CC
Current
–100 mA
+100 mA
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
11
14
pF
C
OUT
Output Capacitance
V
OUT
= 0
12
16
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
14
16
pF
C
IN3
WP#/ACC Pin Capacitance
V
IN
= 0
17
20
pF
相關(guān)PDF資料
PDF描述
AM50DL128BH85IS Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128CG70IS 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM
AM50DL128CG70IT 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM
AM50DL128CG85IS 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM
AM50DL128CG85IT 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM50DL128BH85IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories
AM50DL128BH85IT 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories
AM50DL128CG 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128CG70IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128CG70IT 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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