參數(shù)資料
型號(hào): AM50DL128BH85I
廠商: Advanced Micro Devices, Inc.
元件分類: SRAM
英文描述: Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述: 堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁(yè)數(shù): 60/68頁(yè)
文件大?。?/td> 959K
代理商: AM50DL128BH85I
58
Am50DL128BH
October 7, 2003
A D V A N C E I N F O R M A T I O N
pSRAM AC CHARACTERISTICS
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
Figure 32.
Pseudo SRAM Write Cycle—CE#1ps Control
t
WC
Valid Data In
t
AS
t
CH
Addresses
A20 to A0
CE#1ps
CE2ps
WE#
LB#, UB#
D
IN
DQ15 to DQ0
D
OUT
DQ15 to DQ0
t
CW
t
DS
t
DH
t
WP
t
WR
t
CEH
t
BW
t
BE
t
ODW
t
COE
High-Z
High-Z
(Note 1)
(Note 1)
相關(guān)PDF資料
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AM50DL128BH85IS Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128CG70IS 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM
AM50DL128CG70IT 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM
AM50DL128CG85IS 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM
AM50DL128CG85IT 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM
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