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參數(shù)資料
| 型號： | AM50DL128BH70IT |
| 廠商： | Advanced Micro Devices, Inc. |
| 元件分類： | SRAM |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| 中文描述： | 堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 57/68頁 |
| 文件大?。?/td> | 959K |
| 代理商： | AM50DL128BH70IT |
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October 7, 2003
Am50DL128BH
55
A D V A N C E I N F O R M A T I O N
pSRAM AC CHARACTERISTICS
Read Cycle
Notes:
1. t
OD,
t
ODo
, t
BD
, and t
ODW
are defined as the time at which
the outputs achieve the open circuit condition and are
not referenced to output voltage levels.
2. If CE#, LB#, or UB# goes low at the same time or before
WE# goes high, the outputs will remain at high impedance.
3. If CE#, LB#, or UB# goes low at the same time or after WE#
goes low, the outputs will remain at high impedance.
Figure 29.
Psuedo SRAM Read Cycle
Parameter
Symbol
Description
Speed
Unit
56, 70
85
t
RC
t
ACC
t
CO
t
OE
t
BA
t
COE
t
OEE
t
BE
t
OD
t
ODO
t
BD
t
OH
t
PM
t
PC
t
AA
t
AOH
Read Cycle Time
Min
70
85
ns
Address Access Time
Max
70
85
ns
Chip Enable Access Time
Max
70
85
ns
Output Enable Access Time
Max
25
ns
Data Byte Control Access Time
Max
25
ns
Chip Enable Low to Output Active
Min
10
ns
Output Enable Low to Output Active
Min
0
ns
Data Byte Control Low to Output Active
Min
0
ns
Chip Enable High to Output High-Z
Max
20
ns
Output Enable High to Output High-Z
Max
20
ns
Data Byte Control High to Output High-Z
Max
20
ns
Output Data Hold from Address Change
Min
10
ns
Page Mode Time
Min
70
ns
Page Mode Cycle Time
Min
30
ns
Page Mode Address Access Time
Max
30
ns
Page Output Data Hold Time
Min
10
ns
t
RC
t
ACC
Addresses
A20 to A0
CE#1s
CE2s
OE#
WE#
LB#, UB#
D
OUT
DQ15 to DQ0
t
CO
t
OH
Fixed High
High-Z
High-Z
t
OE
t
BA
t
OD
t
ODO
t
BD
Valid Data Out
Indeterminate
t
BE
t
OEE
t
COE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM50DL128BH85I | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128BH85IS | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128CG70IS | 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM |
| AM50DL128CG70IT | 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM |
| AM50DL128CG85IS | 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM50DL128BH85I | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128BH85IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories |
| AM50DL128BH85IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories |
| AM50DL128CG | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128CG70IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
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