參數(shù)資料
型號(hào)： AM50DL128BH70IS
廠商： Advanced Micro Devices, Inc.
元件分類： SRAM
英文描述： Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述： 堆疊式多芯片封裝（MCP）閃存和SRAM
文件頁(yè)數(shù)： 3/68頁(yè)
文件大?。?/td> 959K
代理商： AM50DL128BH70IS
ADVANCE INFORMATION
Am50DL128BH
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous
Operation Flash Memories and 32 Mbit (2 M x 16-Bit) Pseudo Static RAM with Page Mode
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
Publication#
30773
Issue Date:
October 7, 2003
Rev:
A
Amendment/
+1
DISTINCTIVE CHARACTERISTICS
MCP Features
Power supply voltage of 2.7 to 3.3 volt
■
■
High performance
— Access time as fast as 55 ns
Package
— 73-Ball FBGA
Operating Temperature
— –40°C to +85°C
■
■
Flash Memory Features
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
■
Flexible Bank
architecture
— Read may occur in any of the three banks not being written
or erased.
— Four banks may be grouped by customer to achieve desired
bank divisions.
■
Manufactured on 0.13 μm process technology
SecSi (Secured Silicon) Sector: Extra 256 Byte sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
—
Customer lockable:
Sector is one-time programmable. Once
sector is locked, data cannot be changed.
■
Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
■
Boot sectors
— Top and bottom boot sectors in the same device
■
Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
flash standard
■
■
PERFORMANCE CHARACTERISTICS
High performance
— Access time as fast as 55 ns
— Program time: 4 μs/word typical utilizing Accelerate function
■
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■
Minimum 1 million erase cycles guaranteed per sector
■
■
20 year data retention at 125
°
C
— Reliable operation for the life of the system
SOFTWARE FEATURES
Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
■
Supports Common Flash Memory Interface (CFI)
■
■
Program/Erase Suspend/Erase Resume
— Suspends program/erase operations to allow
programming/erasing in same bank
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
■
■
HARDWARE FEATURES
Any combination of sectors can be erased
■
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase cycle
completion
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state machine to
the read mode
WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1, 140, and
141, regardless of sector protect status
— Acceleration (ACC) function accelerates program timing
Sector protection
— Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
■
■
■
pSRAM Features
Power dissipation
— Operating: 40 mA maximum
— Standby: 70 μA maximum
— Deep power-down standby: 5 μA
■
CE1s# and CE2s Chip Select
Power down features using CE1s# and CE2s
Data retention supply voltage: 2.7 to 3.3 volt
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
8-word page mode access
■
■
■
■
■
相關(guān)PDF資料
PDF描述
AM50DL128BH70IT Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128BH85I Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128BH85IS Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128CG70IS 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM
AM50DL128CG70IT 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM50DL128BH70IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128BH85I 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128BH85IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories
AM50DL128BH85IT 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories
AM50DL128CG 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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