參數(shù)資料
型號: AM50DL128BH56IS
廠商: Advanced Micro Devices, Inc.
元件分類: SRAM
英文描述: Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述: 堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 65/68頁
文件大小: 959K
代理商: AM50DL128BH56IS
October 7, 2003
Am50DL128BH
63
A D V A N C E I N F O R M A T I O N
pSRAM ADDRESS SKEW
Figure 36.
Read Address Skew
Note:
If multiple invalid address cycles shorter than t
RC
min occur for a period greater than 10 μs, at least one valid address
cycle over t
RC min
is required during that period.
Figure 37.
Write Address Skew
Note:
If multiple invalid address cycles shorter than t
WC
min occur for a period greater than 10 μs, at least one valid address
cycle over t
WC min
, in addition to t
WP min
, is required during that period.
CE#1s
WE#
Address
t
RC min
over 10
μ
s
CE#1s
WE#
Address
t
WP min
t
WC min
over 10
μ
s
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