參數(shù)資料
型號: AM50DL128BH56IS
廠商: Advanced Micro Devices, Inc.
元件分類: SRAM
英文描述: Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述: 堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 10/68頁
文件大?。?/td> 959K
代理商: AM50DL128BH56IS
8
Am50DL128BH
October 7, 2003
A D V A N C E I N F O R M A T I O N
PIN DESCRIPTION
A20–A0
= 21 Address Inputs (Common)
A21, A-1
= 2 Address Inputs (Flash)
DQ15–DQ0
= 16 Data Inputs/Outputs (Common)
CE#f1
= Chip Enable 1 (Flash 1)
CE#f2
= Chip Enable 2 (Flash 2)
CE#1s
= Chip Enable 1 (pSRAM)
CE2s
= Chip Enable 2 (pSRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output
UB#s
= Upper Byte Control (pSRAM)
LB#s
= Lower Byte Control (pSRAM)
CIOf
= I/O Configuration (Flash)
CIOf = V
IH
= Word mode (x16),
CIOf = V
IL
= Byte mode (x8)
= Hardware Reset Pin, Active Low
RESET#
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
V
CC
f
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
V
CC
s
V
SS
NC
= pSRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
LOGIC SYMBOL
21
16 or 8
DQ15–DQ0
A20–A0
CE#f1
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
SA
A21, A-1
LB#s
CIOf
CE#1s
CE2s
CE#f2
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AM50DL128BH56IT Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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相關代理商/技術參數(shù)
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AM50DL128BH56IT 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories
AM50DL128BH70I 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128BH70IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories
AM50DL128BH70IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128BH85I 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM