參數(shù)資料
型號: AM50DL128BH56IS
廠商: Advanced Micro Devices, Inc.
元件分類: SRAM
英文描述: Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述: 堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 64/68頁
文件大?。?/td> 959K
代理商: AM50DL128BH56IS
62
Am50DL128BH
October 7, 2003
A D V A N C E I N F O R M A T I O N
pSRAM DATA RETENTION
Notes:
1. CE1#s
V
CC
– 0.2 V, CE2s
V
CC
– 0.2 V (CE1#s controlled) or CE2s
0.2 V (CE2s controlled).
2. Typical values are not 100% tested.
pSRAM POWER ON AND DEEP POWER DOWN
Figure 34.
Deep Power-down Timing
Note:
Data cannot be retained during deep power-down standby mode.
Figure 35.
Power-on Timing
Parameter
Symbol
Parameter Description
Test Setup
Min
Typ
Max
Unit
V
DR
V
CC
for Data Retention
CS1#s
V
CC
– 0.2 V (Note 1)
V
CC
= 3.0 V, CE1#s
V
CC
– 0.2 V
(Note 1)
2.7
3.3
V
I
DR
Data Retention Current
1.0
(Note 2)
70
μA
t
CS
t
CH
t
DPD
t
CHC
t
CHP
CE2 Setup Time
0
ns
CE2 Hold Time
300
μs
CE2 Pulse Width
10
ms
CE2 Hold from CE#1
0
ns
CE2 Hold from Power On
30
μs
CE#1s
CE#2s
t
DPD
t
CH
t
CS
CE#1s
V
DD
CE#2s
t
CHC
t
CHP
t
CH
V
DD min
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