參數資料
型號： AM45DL3238GB85IT
廠商： SPANSION LLC
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 8 X 11.60 MM, FBGA-73
文件頁數： 6/64頁
文件大?。?/td> 1191K
代理商： AM45DL3238GB85IT
August 28, 2002
Am45DL32x8G
13
PR ELI M I NARY
Table 4.
Device Bus Operations—Flash Byte Mode, CIOf = V
IL; CC SRAM Byte Mode, CIOs = VSS
Legend: L = Logic Low = V
IL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = CC SRAM
Address Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In (for Flash Byte Mode, DQ15 = A-1), DIN = Data In,
DOUT = Data Out, CC = CompactCell
TM
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = V
IL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = V
IL, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = V
ACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
6. If WP#/ACC = V
IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and
Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
FLASH DEVICE BUS OPERATIONS
Word/Byte Configuration
The CIOf pin controls whether the device data I/O pins
operate in the byte or word configuration. If the CIOf
pin is set at logic ‘1’, the device is in word configura-
tion, DQ15–DQ0 are active and controlled by CE#f
and OE#.
If the CIOf pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ7–DQ0 are
active and controlled by CE#f and OE#. The data I/O
pins DQ14–DQ8 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE#f and OE# pins to V
IL. CE#f is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
IH . T he CIO f pin determi nes
Operation
(Notes 1, 2)
CE#f CE1#s CE2s OE# WE#
SA
Addr.
LB#s
UB#s
RESET#
WP#/ACC
DQ7–
DQ0
DQ15–
DQ8
Read from Flash
L
HX
LH
X
A
IN
XX
H
L/H
D
OUT
High-Z
XL
Write to Flash
L
HX
HL
X
A
IN
XX
H
D
IN
High-Z
XL
Standby
VCC ±
0.3 V
HX
XX
X
VCC ±
0.3 V
H
High-Z
XL
Output Disable
H
L
H
SA
X
H
L/H
High-Z
Flash Hardware
Reset
X
HX
X
L
L/H
High-Z
XL
Sector Protect
L
HX
HL
X
SADD,
A6 = L,
A1 = H,
A0 = L
XX
V
ID
L/H
D
IN
X
XL
Sector Unprotect
L
HX
HL
X
SADD,
A6 = L,
A1 = H,
A0 = L
XX
V
ID
D
IN
X
XL
Temporary
Sector Unprotect
X
HX
XX
X
A
IN
XX
V
ID
D
IN
High-Z
XL
Read from SRAM
H
L
H
L
H
SA
A
IN
XX
H
X
D
OUT
High-Z
Write to SRAM
H
L
H
X
L
SA
A
IN
XX
H
X
D
IN
High-Z
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