
August 28, 2002
Am45DL32x8G
9
PR ELI M I NARY
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Valid Combinations
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables
1-3 lists the device bus operations, the
inputs and control levels they require, and the result-
ing output. The following subsections describe each of
these operations in further detail.
Am45DL32x
8
G
T
70
I
T
TAPE AND REEL
T=
7 inches
S
=
13 inches
TEMPERATURE RANGE
I
=
Industrial (–40
°C to +85°C)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT SECTOR ARCHITECTURE
T=
Top Boot
B
=
Bottom Boot
PROCESS TECHNOLOGY
G
=
0.17 m
COMPACTCELL SRAM DEVICE DENSITY
8=
8 Mbits
AMD DEVICE NUMBER/DESCRIPTION
Am45DL32x8G
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL32xG 32 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation
Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) CompactCell
TM Static RAM
Valid Combinations
Order Number
Package Marking
Am45DL3228GT70I
Am45DL3228GB70I
T, S
M45000000S
M45000000T
Am45DL3228GT85I
Am45DL3228GB85I
M45000000U
M45000000V
Am45DL3238GT70I
Am45DL3238GB70I
M45000001C
M45000001D
Am45DL3238GT85I
Am45DL3238GB85I
M45000001E
M45000001F
Am45DL3248GT70I
Am45DL3248GB70I
M45000001W
M45000001X
Am45DL3248GT85I
Am45DL3248GB85I
M45000001Y
M45000001Z