參數(shù)資料
型號: AM42DL640AG
英文描述: 200NS, CERDIP, 883C; LEV B COMPLIANT(EEPROM)
中文描述: Am42DL640AG -堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 43/60頁
文件大?。?/td> 956K
代理商: AM42DL640AG
42
Am42DL16x2D
March 4, 2002
P R E L I M I N A R Y
AC CHARACTERISTICS
Flash Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
Parameter
Speed Options
Unit
JEDEC
Std
Description
Min
70
85
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
70
85
ns
t
AVWL
t
AS
Address Setup Time (WE# to Address)
Min
0
ns
t
ASO
Address Setup Time to OE# or
CE#f
low during toggle bit
polling
Min
15
ns
t
WLAX
t
AH
Address Hold Time (WE# to Address)
Min
45
ns
t
AHT
Address Hold Time From CE#f or OE# high during toggle bit
polling
Min
0
ns
t
DVWH
t
DS
Data Setup Time
Min
35
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OEH
OE# Hold Time
Read
Min
0
ns
Toggle and Data# Polling
Min
10
ns
t
OEPH
Output Enable High during toggle bit polling
Min
20
ns
t
GHEL
t
GHEL
Read Recovery Time Before Write (OE# High to CE#f Low)
Min
0
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time (CE#f to WE#)
Min
0
ns
t
ELWL
t
CS
CE#f Setup Time (WE# to CE#f)
Min
0
ns
t
EHWH
t
WH
WE# Hold Time (CE#f to WE#)
Min
0
ns
t
WHEH
t
CH
CE#f Hold Time (CE#f to WE#)
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
30
35
ns
t
ELEH
t
CP
CE#f Pulse Width
Min
30
35
ns
t
WHDL
t
WPH
Write Pulse Width High
Min
0
ns
t
SR/W
Latency Between Read and Write Operations
Min
0
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 2)
Typ
7
μs
t
WHWH1
t
WHWH1
Accelerated Programming Operation (Note 2)
Typ
4
μs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
0.7
sec
t
VCS
V
CC
f Setup Time (Note 1)
Min
50
μs
t
RB
Write Recovery Time from RY/BY#
Min
0
ns
t
BUSY
Program/Erase Valid to RY/BY# Delay
Max
90
ns
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