參數(shù)資料
型號: AM41PDS3228D
英文描述: 150NS, CERDIP, 883C; LEV B COMPLIANT(EEPROM)
中文描述: 32兆位(2米× 16位)的CMOS電壓1.8只。同時采取行動,頁面模式閃存和8兆位(1 M中的x 8-Bit/512畝x 16位),靜態(tài)存儲器(初步)
文件頁數(shù): 51/59頁
文件大?。?/td> 1068K
代理商: AM41PDS3228D
50
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
SRAM AC CHARACTERISTICS
Read Cycle
Note:
CE1#s = OE# = V
IL
, CE2s = WE# = V
IH
, UB#s and/or LB#s = V
IL
Figure 28.
SRAM Read Cycle—Address Controlled
Parameter
Symbol
Description
10, 11
Unit
t
RC
Read Cycle Time
Min
70
ns
t
AA
Address Access Time
Max
70
ns
t
CO1
, t
CO2
Chip Enable to Output
Max
70
ns
t
OE
Output Enable Access Time
Max
35
ns
t
BA
LB#s, UB#s to Access Time
Max
70
ns
t
LZ1
, t
LZ2
Chip Enable (CE1#s Low and CE2s High) to Low-Z Output
Min
10
ns
t
BLZ
UB#, LB# Enable to Low-Z Output
Min
10
ns
t
OLZ
Output Enable to Low-Z Output
Min
5
ns
t
HZ1
, t
HZ2
Chip Disable to High-Z Output
Max
25
ns
t
BHZ
UB#s, LB#s Disable to High-Z Output
Max
25
ns
t
OHZ
Output Disable to High-Z Output
Max
25
ns
t
OH
Output Data Hold from Address Change
Min
10
ns
Address
Data Out
Previous Data Valid
Data Valid
t
AA
t
RC
t
OH
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