參數(shù)資料
型號(hào): AM41PDS3224DT11IT
廠商: SPANSION LLC
元件分類: 存儲(chǔ)器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA73
封裝: 8 X 11.60 MM, FBGA-73
文件頁(yè)數(shù): 37/59頁(yè)
文件大小: 1072K
代理商: AM41PDS3224DT11IT
May 13, 2002
Am41PDS3224D
41
P R E L IMINARY
FLASH AC CHARACTERISTICS
Flash Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
Parameter
Speed Options
Unit
JEDEC
Std
Description
10
11
tAVAV
tWC
Write Cycle Time (Note 1)
Min
100
110
ns
t
AVWL
t
AS
Address Setup Time (WE# to Address)
Min
0
ns
t
ASO
Address Setup Time to OE# or
CE#f Low During Toggle Bit
Polling
Min
15
ns
tWLAX
tAH
Address Hold Time (WE# to Address)
Min
60
ns
t
AHT
Address Hold Time From CE#f or OE# High During Toggle Bit
Polling
Min
0
ns
tDVWH
tDS
Data Setup Time
Min
60
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
tOEH
OE# Hold Time
Read
Min
0
ns
Toggle and Data# Polling
Min
20
ns
tOEPH
Output Enable High During Toggle Bit Polling
Min
20
ns
t
GHEL
t
GHEL
Read Recovery Time Before Write (OE# High to CE#f Low)
Min
0
ns
tGHWL
Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time (CE#f to WE#)
Min
0
ns
tELWL
tCS
CE#f Setup Time (WE# to CE#f)
Min
0
ns
t
EHWH
t
WH
WE# Hold Time (CE#f to WE#)
Min
0
ns
tWHEH
tCH
CE#f Hold Time (CE#f to WE#)
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
60
ns
tELEH
tCP
CE#f Pulse Width
Min
60
ns
t
WHDL
t
WPH
Write Pulse Width High
Min
60
ns
tSR/W
Latency Between Read and Write Operations
Min
0
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 2)
Typ
11
s
t
WHWH1
t
WHWH1
Accelerated Programming Operation,
Word or Byte (Note 2)
Typ
5
s
tWHWH2
Sector Erase Operation (Note 2)
Typ
1
sec
t
VCS
V
CCf Setup Time (Note 1)
Min
50
s
tRB
Write Recovery Time From RY/BY#
Min
0
ns
t
BUSY
Program/Erase Valid To RY/BY# Delay
Max
90
ns
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