參數(shù)資料
型號： AM41DL32X8G
英文描述： 200NS, LCC, IND TEMP(EEPROM)
中文描述： Am41DL32x8G -堆疊式多芯片封裝（MCP）閃存和SRAM
文件頁數(shù)： 4/63頁
文件大小： 1052K
代理商： AM41DL32X8G
Am41DL16x4D
3
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .7
Special Handling Instructions for FBGA Package ....................7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V
IH
;
SRAM Word Mode, CIOs = V
CC
..................................................... 11
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
;
SRAM Byte Mode, CIOs = V
SS
......................................................12
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SS
;
SRAM Word Mode, CIOs = V
CC
.....................................................13
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
IL
; SRAM
Byte Mode, CIOs = V
..................................................................14
Word/Byte Configuration ....................................................... 15
Requirements for Reading Array Data ...................................15
Writing Commands/Command Sequences ............................15
Accelerated ProgramOperation ..........................................15
Autoselect Functions ...........................................................15
Simultaneous Read/Write Operations with Zero Latency .......15
Standby Mode ........................................................................ 16
Automatic Sleep Mode ...........................................................16
RESET#: Hardware Reset Pin ...............................................16
Output Disable Mode ..............................................................16
Table 5. Device Bank Division ........................................................16
Table 6. Sector Addresses for Top Boot Sector Devices ............... 17
Table 7. SecSi Sector Addresses for Top Boot Devices ................17
Table 8. Sector Addresses for BottomBoot Sector Devices ...........18
Table 9. SecSi
Addresses for BottomBoot Devices ..................18
Autoselect Mode .....................................................................19
Table 10. Top Boot Sector/Sector Block Addresses for Protection/Un-
protection ........................................................................................19
Table 11. BottomBoot Sector/Sector Block Addresses
forProtection/Unprotection .............................................................19
Write Protect (WP#) ................................................................19
Temporary Sector/Sector Block Unprotect .............................20
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-SystemSector/Sector Block Protect and Unprotect Algo-
rithms.............................................................................................. 21
SecSi (Secured Silicon) Sector Flash Memory Region ..........22
Factory Locked: SecSi Sector Programmed and Protected At
the Factory ..........................................................................22
Customer Lockable: SecSi Sector NOT Programmed or Pro-
tected At the Factory ...........................................................22
Hardware Data Protection ......................................................22
Low V
CC
Write Inhibit ...........................................................22
Write Pulse
“
Glitch
”
Protection ............................................23
Logical Inhibit ......................................................................23
Power-Up Write Inhibit .........................................................23
Common Flash Memory Interface (CFI) . . . . . . .23
Table 12. CFI Query Identification String........................................ 23
SystemInterface String................................................................... 24
Table 14. Device Geometry Definition............................................ 24
Table 15. Primary Vendor-Specific Extended Query...................... 25
Command Definitions . . . . . . . . . . . . . . . . . . . . . .26
Reading Array Data ................................................................26
Reset Command .....................................................................26
Autoselect Command Sequence ............................................26
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..27
Byte/Word ProgramCommand Sequence .............................27
Unlock Bypass Command Sequence ..................................27
Figure 3. ProgramOperation......................................................... 28
Chip Erase Command Sequence ...........................................28
Sector Erase Command Sequence ........................................28
Erase Suspend/Erase Resume Commands ...........................29
Figure 4. Erase Operation.............................................................. 29
Table 16. Command Definitions (Flash Word Mode)...................... 30
Table 17. Autoselect Device IDs (Word Mode) .............................. 30
Table 18. Command Definitions (Flash Byte Mode)....................... 31
Table 19. Autoselect Device IDs (Byte Mode) ...............................31
Write Operation Status . . . . . . . . . . . . . . . . . . . . 32
DQ7: Data#Polling .................................................................32
Figure 5. Data#Polling Algorithm.................................................. 32
RY/BY# Ready/Busy#............................................................33
DQ6: Toggle Bit I ....................................................................33
Figure 6. Toggle Bit Algorithm........................................................ 33
DQ2: Toggle Bit II ...................................................................34
Reading Toggle Bits DQ6/DQ2 ...............................................34
DQ5: Exceeded Timng Limts ................................................34
DQ3: Sector Erase Timer .......................................................34
Table 20. Write Operation Status ...................................................35
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 36
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 36
Industrial (I) Devices ............................................................36
V
CC
f/V
CC
s Supply Voltage ...................................................36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
CMOS Compatible ..................................................................37
SRAM DC and Operating Characteristics . . . . . 38
Zero-Power Flash .................................................................39
Figure 9. I
CC1
Current vs. Time (Showing Active and Automatic Sleep
Currents)........................................................................................ 39
Figure 10. Typical I
vs. Frequency............................................ 39
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. Test Setup.................................................................... 40
Table 21. Test Specifications .........................................................40
Key To Switching Waveforms . . . . . . . . . . . . . . . 40
Figure 12. Input Waveforms and Measurement Levels................. 40
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
SRAMCE#s Timng ................................................................41
Figure 13. Timng Diagramfor Alternating Between
SRAM to Flash............................................................................... 41
Flash Read-Only Operations .................................................42
Figure 14. Read Operation Timngs............................................... 42
Hardware Reset (RESET#) ....................................................43
Figure 15. Reset Timngs............................................................... 43
Flash Word/Byte Configuration (CIOf) ....................................44
Figure 16. CIOf Timngs for Read Operations................................ 44
Figure 17. CIOf Timngs for Write Operations................................ 44
Flash Erase and ProgramOperations ....................................45
Figure 18. ProgramOperation Timngs.......................................... 46
Figure 19. Accelerated ProgramTimng Diagram.......................... 46
Figure 20. Chip/Sector Erase Operation Timngs.......................... 47
Figure 21. Back-to-back Read/Write Cycle Timngs...................... 48
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM41DL6408G 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM41DL6408G25IS 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
AM41DL6408G25IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
AM41DL6408G30IS 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
AM41DL6408G30IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
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