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參數資料
| 型號： | AM30LV0064DJ40F2IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology |
| 中文描述： | 8M X 8 FLASH 3V PROM, 35 ns, PDSO40 |
| 封裝： | REVERSE, MO-024AC, TSOP2-44/40 |
| 文件頁數： | 23/41頁 |
| 文件大?。?/td> | 1067K |
| 代理商： | AM30LV0064DJ40F2IT |
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Am30LV0064D
23
Erase Operations
Block Erase (60h) (D0h)
The Block Erase command sequence is a two com-
mand operation procedure that must be performed to
erase information in one of the 16 page Flash blocks.
After the first command cycle, two address cycles are
used to input the block address for the block to be
erased. Since the block address only requires address
bits A22–A13 to determine the block address, bits
A12–A9 are don’t care. After the two address cycles
are complete, the second command cycle is issued.
Upon the rising edge of the final WE# pulse for the
second command cycle, the Flash device will begin
the Block Erase operation.
A block typically erases in the Flash array in 2 ms or
less and is guaranteed to erase within 10 ms. The
Flash device appears busy during the Block Erase op-
eration and either the RY/BY# signal or the status
register may be used to monitor completion of the
erase. Only the Erase Suspend, Reset, and Read Sta-
tus commands are valid during the period that the device
is busy.
After erasing a block, the status register bit I/O0
should be checked to verify that the erase operation
completed properly. Figure 10 shows the simplified
timing for Block Erase.
Figure 10. Block Erase
Erase Suspend (B0h) (Superset Command)
The Erase Suspend command sequence is only valid
during a Block Erase operation. Upon the rising edge
of the command WE# pulse, the Flash device will sus-
pend the Block Erase operation. Either the RY/BY#
signal or the status register may be used to determine
when the Block Erase has actually been suspended.
Once the Erase Suspend has taken effect, read or
program operations may be performed in blocks that
are not selected for erasure.
Once a Block Erase has been suspended, the sus-
pended Block Erase operation must be completed
before another block can be selected for erasure.
When the Erase Suspend command is issued, the
Block Erase command is inhibited. The Block Erase
will be invalid until an Erase Resume command allows
the suspended erase to complete, the device is reset,
or power is removed from the device. Refer to Figure
11 for a simplified timing diagram showing the se-
quence of events required to implement Erase
Suspend during a block erase operation. This is an
AMD superset command which is not available on
competitive devices in the marketplace.
Erase Resume (D0h) (Superset Command)
The Erase Resume command sequence is only valid
during an Erase Suspend operation. Upon the rising
CE#
CLE
ALE
WE#
RE#
I/O7-0
SE#
RY/BY#
CMD
Block Address
Block Erase
Block Erase Setup (60h)
CMD
Block Erase (D0h)
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| AM30LV0064DJ40WGIT | 64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology |
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相關代理商/技術參數 |
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| AM30LV0064DJ40WGI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NAND Flash EEPROM |
| AM30LV0064DJ40WGIT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology |
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