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參數(shù)資料
| 型號： | AM30LV0064DJ40F2IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology |
| 中文描述： | 8M X 8 FLASH 3V PROM, 35 ns, PDSO40 |
| 封裝： | REVERSE, MO-024AC, TSOP2-44/40 |
| 文件頁數(shù)： | 17/41頁 |
| 文件大?。?/td> | 1067K |
| 代理商： | AM30LV0064DJ40F2IT |
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Am30LV0064D
17
Gapless Read (02h) (Superset Command)
The Gapless Read command is almost identical to the
Read Data command, except that it allows reading
from multiple pages with only one 7 μs latency occur-
ring on the first page transfer. After the command
cycle is used to write the Gapless Read op-code to the
device, three address cycles are used to input the
starting address for the Gapless Read operation.
The Gapless Read operation requires that the address
entered specifies an address location in the first half of
the selected page. Upon the rising edge of the final
WE# pulse there is a 7 μs latency in which 528 bytes
of information are transferred from the Flash array
page to the 528 byte Data Register. During this 7 μs
period the device will appear busy and either the
RY/BY# signal or the status register may be used to
monitor the completion of the data transfer. Only the
Reset and Read Status commands are valid during
the period that the device is busy. Once the informa-
tion has been loaded into the Data Register, it may be
sequentially read with consecutive 50 ns RE# pulses.
Each RE# pulse will automatically advance the column
address by one. Once the last column has been read,
the page address will automatically increment by one
and the Data Register will be updated with the new
page.
In the case of the Gapless Read, there is no 7 μs la-
tency period encountered when moving from the
current page to the next sequential page.
During the sequential read mode, if the Spare Area
Enable input (SE#) is high, the column address will ad-
vance to address 511 and then the page address will
increment by one. If the SE# input is low, the column
address will advance to address 527 before the page
address is incremented. This allows information in the
Spare Area to be read at the end of the page before
the next page of information is transferred into the
Data Registers.
This is an AMD superset command which is not avail-
able on competitive devices in the marketplace.
Notes:
1. CE# is don’t care in between WE# and RE# transitions.
2. Falling edge of CE# to valid data must be >45 ns.
3. CE# transition when RY/BY# is low terminates read operation.
4. ALE must remain high for entire address latch operation; no transitions allowed.
Figure 3. Gapless Read
CE#
CLE
ALE
WE#
RE#
I/O7-0
SE#
RY/BY#
CMD
Start Address
Read Page
Read Next Page
Read Next Page
Data Transfer
Gapless Read (02h)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM30LV0064DJ40WGIT | 64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology |
| AM33C93A | LJT 16C 16#16 SKT RECP |
| AM3F-1205SH30 | 3 watt dc-dc converters |
| AM3F | 3 watt dc-dc converters |
| AM3F-0503S | 3 watt dc-dc converters |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM30LV0064DJ40WGI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NAND Flash EEPROM |
| AM30LV0064DJ40WGIT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology |
| AM30N02-40D | 制造商:ANALOGPOWER 制造商全稱:ANALOGPOWER 功能描述:N-Channel 20-V (D-S) MOSFET |
| AM30N02-59D | 制造商:ANALOGPOWER 制造商全稱:ANALOGPOWER 功能描述:N-Channel 20-V (D-S) MOSFET |
| AM30N03-40D | 制造商:ANALOGPOWER 制造商全稱:ANALOGPOWER 功能描述:N-Channel 30-V (D-S) MOSFET |
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