參數(shù)資料
型號(hào)： AM29LV128ML93FI
廠商： Advanced Micro Devices, Inc.
英文描述： 128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control
中文描述： 128兆位（8 M中的x 16-Bit/16 M中的x 8位）的MirrorBit⑩3.0伏特，只有統(tǒng)一部門閃存與VersatileI內(nèi)存/ O控制
文件頁(yè)數(shù)： 13/65頁(yè)
文件大?。?/td> 1222K
代理商： AM29LV128ML93FI
September 9, 2003
Am29LV128MH/L
11
D A T A S H E E T
V
IH
.) If CE# and RESET# are held at V
IH
, but not within
V
IO
± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device re-
quires standard access time (t
CE
) for read access
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Refer to the DC Characteristics table for the standby
current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Refer to the DC Characteristics table for the automatic
sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 16 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high
impedance state.
相關(guān)PDF資料
PDF描述
AM29LV128ML93EI LM3704/LM3705 Microprocessor Supervisory Circuits with Power Fail Input, Low Line Output and Manual Reset; Package: MINI SOIC; No of Pins: 10; Qty per Container: 1000; Container: Reel
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