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參數資料
| 型號： | AM29F080B-70SI |
| 英文描述： | x8 Flash EEPROM |
| 中文描述： | x8閃存EEPROM的 |
| 文件頁數： | 11/39頁 |
| 文件大?。?/td> | 728K |
| 代理商： | AM29F080B-70SI |
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Am29F002B/Am29F002NB
11
Sector protection/unprotection must be implemented
using programming equipment. The procedure
requires a high voltage (V
ID
) on address pin A9 and the
control pins. Details on this method are provided in the
supplements, publication numbers 20819
(Am29F002B) and 21183 (Am29F002NB). Contact an
AMD representative to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
Note:
This feature requires the RESET# pin and is
therefore not available on the Am29F002NB.
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the
RESET# pin to V
ID
. During this mode, formerly pro-
tected sectors can be programmed or erased by
selecting the sector addresses. Once V
ID
is removed
from the RESET# pin, all the previously protected
sectors are protected again. Figure 1 shows the algo-
rithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
Figure 1.
Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by
spurious system level signals during V
CC
power-up and
power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not
accept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect
Completed (Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
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