參數(shù)資料
型號(hào)： AM29BDS320GBD3VMF
廠商： SPANSION LLC
元件分類： PROM
英文描述： 2M X 16 FLASH 1.8V PROM, 70 ns, PBGA64
封裝： 8 X 9 MM, 0.80 MM PITCH, FBGA-64
文件頁(yè)數(shù)： 34/75頁(yè)
文件大?。?/td> 1075K
代理商： AM29BDS320GBD3VMF
2
Am29BDS320G
27243B2 May 15, 2007
Data
Sheet
General Description
The Am29BDS320G is a 32 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst
Mode Flash memory device, organized as 2,097,152 words of 16 bits each. This
device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the mem-
ory array. The device supports Enhanced VIO to offer up to 3V compatible inputs
and outputs. A 12.0-volt VID may be used for faster program performance if de-
sired. The device can also be programmed in standard EPROM programmers.
At 54 MHz, the device provides a burst access of 13.5 ns at 30 pF with a latency
of 87.5 ns at 30 pF. At 40 MHz, the device provides a burst access of 20 ns at 30
pF with a latency of 95 ns at 30 pF. The device operates within the industrial tem-
perature range of -40°C to +85°C. The device is offered in the 64-ball FBGA
package.
The Simultaneous Read/Write architecture provides simultaneous operation
by dividing the memory space into four banks. The device can improve overall
system performance by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from another bank, with zero latency.
This releases the system from waiting for the completion of program or erase
operations.
The device is divided as shown in the following table:
The Enhanced VersatileIO (VIO) control allows the host system to set the volt-
age levels that the device generates at its data outputs and the voltages tolerated
at its data inputs to the same voltage level that is asserted on the VIO pin. This
allows the device to operate in 1.8 V and 3 V system environments as required.
The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#)
and Output Enable (OE#) to control asynchronous read and write operations. For
burst operations, the device additionally requires Ready (RDY), and Clock (CLK).
This implementation allows easy interface with minimal glue logic to a wide range
of microprocessors/microcontrollers for high performance read operations.
The burst read mode feature gives system designers flexibility in the interface to
the device. The user can preset the burst length and wrap through the same
memory space, or read the flash array in continuous mode.
The clock polarity feature provides system designers a choice of active clock
edges, either rising or falling. The active clock edge initiates burst accesses and
determines when data will be output.
The device is entirely command set compatible with the JEDEC 42.4 single-
power-supply Flash standard. Commands are written to the command regis-
ter using standard microprocessor write timing. Register contents serve as inputs
to an internal state-machine that controls the erase and programming circuitry.
Bank
Quantity
Size
A
48 Kwords
15
32 Kwords
B
16
32 Kwords
C
16
32 Kwords
D
15
32 Kwords
48 Kwords
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