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參數(shù)資料
| 型號： | AM29BDS320GBD3VMF |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 1.8V PROM, 70 ns, PBGA64 |
| 封裝： | 8 X 9 MM, 0.80 MM PITCH, FBGA-64 |
| 文件頁數(shù)： | 20/75頁 |
| 文件大?。?/td> | 1075K |
| 代理商： | AM29BDS320GBD3VMF |
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May 15, 2007 27243B2
Am29BDS320G
25
Data
Sheet
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 14, “Command Definitions,” on page 36
defines the valid register command sequences. Note that writing incorrect ad-
dress and data values or writing them in the improper sequence may place the
device in an unknown state. A reset command is required to return the device to
normal operation.
Refer to the AC Characteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data in asynchronous mode. Each bank is
ready to read array data after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank
enters the erase-suspend-read mode, after which the system can read data from
any non-erase-suspended sector within the same bank. After completing a pro-
gramming operation in the Erase Suspend mode, the system may once again
read array data with the same exception. See the “Erase Suspend/Erase Resume
Commands” section on page 34 section for more information.
The system must issue the reset command to return a bank to the read (or erase-
suspend-read) mode if DQ5 goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the “Reset Command” section
on page 30 section for more information.
quirements for Synchronous (Burst) Read Operation” sections for more
information. The Asynchronous Read and Synchronous/Burst Read tables provide
Set Burst Mode Configuration Register Command Sequence
The device uses a burst mode configuration register to set the various burst pa-
rameters: number of wait states, burst read mode, active clock edge, RDY
configuration, and synchronous mode active. The burst mode configuration reg-
ister must be set before the device will enter burst mode.
The burst mode configuration register is loaded with a three-cycle command se-
quence. The first two cycles are standard unlock sequences. On the third cycle,
the data should be C0h, address bits A11–A0 should be 555h, and address bits
A19–A12 set the code to be latched. The device will power up or after a hardware
reset with the default setting, which is in asynchronous mode. The register must
be set before the device can enter synchronous mode. The burst mode configu-
ration register can not be changed during device operations (program, erase, or
sector lock).
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