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參數(shù)資料
| 型號(hào)： | AK4641 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16 BIT CODEC WITH BLUETOOTH INTERFACE |
| 中文描述： | 16位編解碼器與藍(lán)牙接口 |
| 文件頁數(shù)： | 9/51頁 |
| 文件大?。?/td> | 461K |
| 代理商： | AK4641 |
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ASAHI KASEI
[AK4641]
MS0301-E-00
2004/05
- 17 -
The clock required to operate are MCLK, LRCK (fs) and BICK (
≥ 32fs). Then the master clock (MCLK) should be
synchronized with LRCK. The phase between these clocks does not matter.
The S/N of the DAC of Stereo CODEC at low sampling frequencies is worse than at high sampling frequencies due to
out-of-band noise. The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the
DAC output of Stereo CODEC through Headphone amp at fs=8kHz is shown in Table 3.
MCK1
MCK0
Sampling Frequency
(fs)
MCLK
0
7kHz
48kHz
256fs
Default
0
1
7kHz
24kHz
512fs
1
0
7kHz
12kHz
1024fs
1
-
N/A
Table 2. Select Master Clock Frequency
MCLK
S/N (fs=8kHz, A-weighted)
256fs
82dB
512fs
90dB
1024fs
90dB
Table 3. Relationship between MCLK and S/N of Line Out
When the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4641 may
occur pop noise.
All external clocks (MCLK, BICK and LRCK) should always be present when either ADC or DAC of Stereo CODEC is
power-up. If these clocks are not provided, the AK4641 may draw excess current and it is not possible to operate properly
because utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4641 should be in the
power-down mode.
Power up
Power down
BICK pin
Input
Fixed to “L” or “H” externally
LRCK pin
Input
Fixed to “L” or “H” externally
Table 4. Clock Operation
System Reset
Upon power-up, reset the AK4641 by bringing the PDN pin = “L”. This ensures that all internal registers are reset to their
initial values.
The ADC of Stereo CODEC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The
initialization cycle time is 2081/fs, or 47.2ms@fs=44.1kHz. During the initialization cycle, the ADC digital data output of
Stereo CODEC is forced to a 2's compliment, “0”. The ADC output of Stereo CODEC reflects the analog input signal
after the initialization cycle is complete. The DAC of Stereo CODEC does not require an initialization cycle.
The ADC of Mono CODEC enters an initialization cycle that starts when the PMAD2 bit is changed from “0” to “1”. The
initialization cycle time is 1057/Bfs, or 132ms@Bfs=8kHz. During the initialization cycle, the ADC digital data output of
Mono CODEC is forced to a 2's compliment, “0”. The ADC output of Mono CODEC reflects the analog input signal after
the initialization cycle is complete. The DAC of Mono CODEC does not require an initialization cycle.
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PDF描述 |
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| AK4641VN | 16 BIT CODEC WITH BLUETOOTH INTERFACE |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4641EN | 制造商:AKM 制造商全稱:AKM 功能描述:16bit stereo CODEC with built-in Microphone-amplifier and 16bit Mono CODEC for Bluetooth Interface. |
| AK4641VN | 制造商:AKM 制造商全稱:AKM 功能描述:16 BIT CODEC WITH BLUETOOTH INTERFACE |
| AK4642 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ???￡ Stereo CODEC with MIC/HP/SPK-AMP |
| AK4642EN | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP/SPK-AMP |
| AK4642VN | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ???￡ Stereo CODEC with MIC/HP/SPK-AMP |
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