參數(shù)資料
型號: AGLP030V5-CS201I
廠商: Microsemi SoC
文件頁數(shù): 32/134頁
文件大小: 0K
描述: IC FPGA IGLOO PLUS 30K 201-CSP
標(biāo)準(zhǔn)包裝: 384
系列: IGLOO PLUS
邏輯元件/單元數(shù): 792
輸入/輸出數(shù): 120
門數(shù): 30000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 201-VFBGA,CSBGA
供應(yīng)商設(shè)備封裝: 201-CSP(8x8)
Revision 16
5-1
5 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each revision of the IGLOO PLUS datasheet.
Revision
Changes
Page
Revision 16
(December 2012)
The "IGLOO PLUS Ordering Information" section has been updated to mention "Y"
as "Blank" mentioning "Device Does Not Include License to Implement IP Based on
the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43175).
IGLOO PLUS CCC/PLL Specification referring the reader to SmartGen was revised
to refer instead to the online help associated with the core (SAR 42566).
Live at Power-Up (LAPU) has been replaced with ’Instant On’.
NA
Revision 15
(October 2012)
Values updated for IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage in
IGLOO PLUS Devices and for IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage
in IGLOO PLUS Devices (SAR 31988). Also added a new Note to the two tables.
Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip
(SoC) throughout the document (SAR 40277).
N/A
Revision 14
(September 2012)
The "Security" section was modified to clarify that Microsemi does not support read-
back of programmed data.
Revision 13
(June 2012)
34843).
Updated the terminology used in Timing Characteristics in the following tables:
The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)"
section in the "Pin Descriptions and Packaging" section: "Within the package, the
VMV plane is decoupled from the simultaneous switching noise originating from the
output buffer VCCI domain" and replaced with “Within the package, the VMV plane
biases the input stage of the I/Os in the I/O banks” (SAR 38320). The datasheet
mentions that "VMV pins must be connected to the corresponding VCCI pins" for an
ESD enhancement.
Revision 12
(March 2012)
were revised to clarify that although no existing security measures can give an
absolute guarantee, Microsemi FPGAs implement the best security available in the
industry (SAR 34664).
The Y security option and Licensed DPA Logo were added to the "IGLOO PLUS
Ordering Information" section. The trademarked Licensed DPA Logo identifies that a
product is covered by a DPA counter-measures license from Cryptography Research
(SAR 34724).
The following sentence was removed from the "Advanced Architecture" section:
"In addition, extensive on-chip programming circuitry allows for rapid, single-voltage
(3.3 V) programming of IGLOO PLUS devices via an IEEE 1532 JTAG interface"
(SAR 34684).
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