2-68 Revision 16 Timing Characteristics 1.5 V DC Core Voltage Table 2-92 RAM4K9
參數(shù)資料
型號(hào): AGLP030V5-CS201I
廠商: Microsemi SoC
文件頁數(shù): 116/134頁
文件大?。?/td> 0K
描述: IC FPGA IGLOO PLUS 30K 201-CSP
標(biāo)準(zhǔn)包裝: 384
系列: IGLOO PLUS
邏輯元件/單元數(shù): 792
輸入/輸出數(shù): 120
門數(shù): 30000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 201-VFBGA,CSBGA
供應(yīng)商設(shè)備封裝: 201-CSP(8x8)
IGLOO PLUS DC and Switching Characteristics
2-68
Revision 16
Timing Characteristics
1.5 V DC Core Voltage
Table 2-92 RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
Std. Units
tAS
Address setup time
0.69
ns
tAH
Address hold time
0.13
ns
tENS
REN, WEN setup time
0.68
ns
tENH
REN, WEN hold time
0.13
ns
tBKS
BLK setup time
1.37
ns
tBKH
BLK hold time
0.13
ns
tDS
Input data (DIN) setup time
0.59
ns
tDH
Input data (DIN) hold time
0.30
ns
tCKQ1
Clock High to new data valid on DOUT (output retained, WMODE = 0)
2.94
ns
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
2.55
ns
tCKQ2
Clock High to new data valid on DOUT (pipelined)
1.51
ns
tC2CWWL1
Address collision clk-to-clk delay for reliable write after write on same address – applicable
to closing edge
0.29
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on same address –
applicable to opening edge
0.24
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on same address –
applicable to opening edge
0.40
ns
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
1.72
ns
RESET Low to data out Low on DOUT (pipelined)
1.72
ns
tREMRSTB
RESET removal
0.51
ns
tRECRSTB
RESET recovery
2.68
ns
tMPWRSTB RESET minimum pulse width
0.68
ns
tCYC
Clock cycle time
6.24
ns
FMAX
Maximum frequency
160 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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