2-10 Revision 17 Power Consumption of Various Internal Resources Table 2-15 Different Componen" />
參數(shù)資料
型號: AGLN250V5-ZVQG100I
廠商: Microsemi SoC
文件頁數(shù): 70/150頁
文件大?。?/td> 0K
描述: IC FPGA NANO 1KB 250K 100VQFP
標(biāo)準(zhǔn)包裝: 90
系列: IGLOO nano
邏輯元件/單元數(shù): 6144
RAM 位總計: 36864
輸入/輸出數(shù): 68
門數(shù): 250000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
IGLOO nano DC and Switching Characteristics
2-10
Revision 17
Power Consumption of Various Internal Resources
Table 2-15 Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices
For IGLOO nano V2 or V5 Devices, 1.5 V Core Supply Voltage
Parameter
Definition
Device Specific Dynamic Power (W/MHz)
AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010
PAC1
Clock contribution of a Global Rib
4.421
4.493
2.700
0
PAC2
Clock contribution of a Global Spine
2.704
1.976
1.982
4.002
2.633
PAC3
Clock contribution of a VersaTile row
1.496
1.504
1.511
1.346
1.340
PAC4
Clock contribution of a VersaTile
used as a sequential module
0.152
0.153
0.148
0.143
PAC5
First contribution of a VersaTile used
as a sequential module
0.057
PAC6
Second contribution of a VersaTile
used as a sequential module
0.207
PAC7
Contribution of a VersaTile used as
a combinatorial module
0.17
PAC8
Average contribution of a routing net
0.7
PAC9
Contribution of an I/O input pin
(standard-dependent)
PAC10
Contribution of an I/O output pin
(standard-dependent)
PAC11
Average contribution of a RAM block
during a read operation
25.00
N/A
PAC12
Average contribution of a RAM block
during a write operation
30.00
N/A
PAC13
Dynamic contribution for PLL
2.70
N/A
Table 2-16 Different Components Contributing to the Static Power Consumption in IGLOO nano Devices
For IGLOO nano V2 or V5 Devices, 1.5 V Core Supply Voltage
Parameter
Definition
Device -Specific Static Power (mW)
AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010
PDC1
Array static power in Active mode
PDC2
Array static power in Static (Idle)
mode
PDC3
Array static power in Flash*Freeze
mode
PDC4 1
Static PLL contribution
1.84
N/A
PDC5
Bank quiescent power
(VCCI-dependent)2
Notes:
1. Minimum contribution of the PLL when running at lowest frequency.
2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet
calculator or the SmartPower tool in Libero SoC.
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