IGLOOe DC and Switching Characteristics
2-16
Revision 13
User I/O Characteristics
Timing Model
Figure 2-3 Timing Model
Operating Conditions: Std. Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case
VCC = 1.425 V, Applicable to 1.5 V DC Core Voltage, V2 and V5 devices
DQ
Y
DQ
Y
Combinational Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
Register Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
LVPECL
LVDS,
BLVDS,
M-LVDS
GTL+ 3.3V
Y
Combinational Cell
Y
Combinational Cell
Y
Combinational Cell
I/O Module
(Non-Registered)
LVTTL/LVCMOS 3.3 V
Output drive strength = 24 mA
High slew rate
I/O Module
(Non-Registered)
LVCMOS 1.5V
Output drive strength = 12 mA
High slew
LVTTL/LVCMOS 3.3 V
Output drive strength = 12 mA
High slew rate
I/O Module
(Non-Registered)
Input LVTTL/LVCMOS 3.3 V
Clock
Input LVTTL/LVCMOS 3.3 V
Clock
Input LVTTL/LVCMOS 3.3 V
Clock
tPD = 1.19 ns
tPD = 1.04 ns
tDP = 1.75 ns
tPD = 1.77 ns
tDP = 3.13 ns
tPD = 1.33 ns
tPD = 0.85 ns
tDP = 2.76 ns
tDP = 3.30 ns
tOCLKQ = 1.02 ns
tDP = 1.85 ns
tOSUD = 0.52 ns
tPY = 1.10 ns
tCLKQ = 0.90 ns
tSUD = 0.82 ns
tPY = 1.10 ns
tPD = 0.90 ns
tCLKQ = 0.90 ns
tSUD = 0.82 ns
tPY = 1.62 ns
tPY = 1.10 ns
tICLKQ = 0.43 ns
tISUD = 0.47 ns
tPY = 1.45 ns