2-100 Revision 13 Applies to 1.2 V DC Core Voltage Table 2-147 RAM4K9 Comm" />
參數(shù)資料
型號： AGLE600V5-FG484
廠商： Microsemi SoC
文件頁數(shù)： 18/166頁
文件大?。?/td> 0K
描述： IC FPGA 1KB FLASH 600K 484-FBGA
標準包裝： 60
系列： IGLOOe
邏輯元件/單元數(shù)： 13824
RAM 位總計： 110592
輸入/輸出數(shù)： 270
門數(shù)： 600000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 484-BGA
供應商設(shè)備封裝： 484-FPBGA（23x23）
IGLOOe DC and Switching Characteristics
2-100
Revision 13
Applies to 1.2 V DC Core Voltage
Table 2-147 RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
Description
Std.
Units
tAS
Address Setup Time
1.53
ns
tAH
Address Hold Time
0.29
ns
tENS
REN, WEN Setup Time
1.50
ns
tENH
REN, WEN Hold Time
0.29
ns
tBKS
BLK Setup Time
3.05
ns
tBKH
BLK Hold Time
0.29
ns
tDS
Input Data (DIN) Setup Time
1.33
ns
tDH
Input Data (DIN) Hold Time
0.66
ns
tCKQ1
Clock High to New Data Valid on DOUT (output retained, WMODE = 0)
6.61
ns
Clock High to New Data Valid on DOUT (flow-through, WMODE = 1)
5.72
ns
tCKQ2
Clock High to New Data Valid on DOUT (pipelined)
3.38
ns
tC2CWWL1
Address collision clk-to-clk delay for reliable write after write on same
address; applicable to closing edge
0.30
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on
same address; applicable to opening edge
0.89
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on
same address; applicable to opening edge
1.01
ns
tRSTBQ
RESET Low to Data Out Low on DOUT (pass-through)
3.86
ns
RESET Low to Data Out Low on DOUT (pipelined)
3.86
ns
tREMRSTB
RESET Removal
1.12
ns
tRECRSTB
RESET Recovery
5.93
ns
tMPWRSTB
RESET Minimum Pulse Width
1.18
ns
tCYC
Clock Cycle Time
10.90
ns
FMAX
Maximum Frequency
92
MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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