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參數(shù)資料
| 型號(hào)： | AGLE3000V2-FGG896I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 35/166頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1KB FLASH 3M 896-FBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | IGLOOe |
| 邏輯元件/單元數(shù)： | 75264 |
| RAM 位總計(jì)： | 516096 |
| 輸入/輸出數(shù)： | 620 |
| 門數(shù)： | 3000000 |
| 電源電壓： | 1.14 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 896-BGA |
| 供應(yīng)商設(shè)備封裝： | 896-FBGA（31x31） |
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IGLOOe Low Power Flash FPGAs
Revision 13
1-7
Pro I/Os with Advanced I/O Standards
The IGLOOe family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V,
1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOOe FPGAs support 19 different I/O standards,
including single-ended, differential, and voltage-referenced. The I/Os are organized into banks, with eight
banks per device (two per side). The configuration of these banks determines the I/O standards
supported. Each I/O bank is subdivided into VREF minibanks, which are used by voltage-referenced
I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line.
Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that
minibank will be able to use that reference voltage.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).
IGLOOe banks support M-LVDS with 20 multi-drop points.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Wide Range I/O Support
IGLOOe devices support JEDEC-defined wide range I/O operation. IGLOOe devices support both the
JESD8-B specification, covering 3.0 V and 3.3 V supplies, for an effective operating range of 2.7 V to
3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from
the board or move to less costly components with greater tolerances. Wide range eases I/O bank
management and provides enhanced protection from system voltage spikes, while providing the flexibility
to easily run custom voltage applications.
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States
During Programming dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.
Select the I/Os you wish to modify (Figure 1-4 on page 1-8).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state
settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the
programming mode, and then held at that value during programming
Z -Tri-State: I/O is tristated
相關(guān)PDF資料 |
PDF描述 |
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| M1AGLE3000V2-FGG896I | IC FPGA 1KB FLASH 3M 896-FBGA |
| 24LC024T-I/SN | IC EEPROM 2KBIT 400KHZ 8SOIC |
| APA1000-PQG208I | IC FPGA PROASIC+ 1M 208-PQFP |
| 24LC024-I/SN | IC EEPROM 2KBIT 400KHZ 8SOIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGLE3000V2-FGG896PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE3000V5-FFG484 | 制造商:Microsemi Corporation 功能描述:FPGA IGLOOE 3M GATES 130NM 1.5V 484FBGA - Trays |
| AGLE3000V5-FFG896 | 制造商:Microsemi Corporation 功能描述:FPGA IGLOOE 3M GATES 130NM 1.5V 896FBGA - Trays |
| AGLE3000V5-FFG896ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE3000V5-FFG896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
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