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參數(shù)資料
| 型號： | AFE8201PFBT |
| 英文描述： | IF Analog-to-Digital Converter with Digital Downconverter |
| 中文描述： | 中頻模擬到數(shù)字轉(zhuǎn)換器與數(shù)字下變頻器 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 220K |
| 代理商： | AFE8201PFBT |
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SBWS016A OCTOBER 2003 REVISED JANUARY 2005
www.ti.com
8
Table 2. Memory Banks
Memory Bank Address
0
1
Description
FIR Filter 1 Coefficients
FIR Filter 2A Coefficients
Size
Data Memory
62 Samples
126 Samples
64 Coefficients
128 Coefficients
2
FIR Filter 2B Coefficients
128 Coefficients
126 Samples
The SPI interface consists of four signals: a serial clock (SCK), an active-low chip select (CS_N), a serial data input
(MOSI—Master Out, Slave In), and a serial data output (MISO—Master In, Slave Out). Data is transferred in groups
of 32 bits. The first 16 bits are the instruction, which indicate:
(1) if data is to be written or to be read;
(2) if the data target is a control register or a memory bank; and
(3) the address of the data target.
The second 16 bits is the data transfer, which is input on MOSI for a write cycle or output on MISO for a read cycle.
A single data word write cycle is shown in Figure 4. The cycle is initiated by the high-to-low transition of the CS_N
line. 32 SCK pulses clock the instruction and the data into the MOSI line. Instructions and data are clocked in MSB
first. The first 16 bits are the instruction; the second 16 bits are the data word. There are two possible single data
word write cycle instructions: register write and memory write. The formats for these instructions are shown in
Figure 5 and Figure 6.
SCK
CS_N
MOSI
MSB
LSB
MISO
Instruction
Data
Figure 4. Single Data Word Control Interface Write Cycle for Registers or Memory
1
0
0
REG_ADDR
Don’t Care
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Figure 5. Register Write Instruction Format
1
0
1
MEM_ADDR
MEM
Don’t Care
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Figure 6. Memory Write Instruction Format
The only information required for a register write is the 5-bit register address (REG_ADDR). For a memory write, the
2-bit memory select (MEM) and the 8-bit memory address (MEM_ADDR) are required.
Following the 16-bit instruction, the 16-bit data word is clocked in, again MSB first. At the end of the write cycle this
data word is written to the appropriate register or memory location in the AFE.
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