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參數(shù)資料
| 型號： | AFE8201PFBT |
| 英文描述： | IF Analog-to-Digital Converter with Digital Downconverter |
| 中文描述： | 中頻模擬到數(shù)字轉換器與數(shù)字下變頻器 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 220K |
| 代理商： | AFE8201PFBT |
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SBWS016A OCTOBER 2003 REVISED JANUARY 2005
www.ti.com
11
DCLKO
DFSO
DOUT0
QA
IA
QB
IB
DOUT1
DFSI
DIN
DAC
MSB
LSB
MSB
MSB
LSB
LSB
Figure 13. Data Interface Timing for MODE = 1
When the data interface receives new outputs from the decimation filters, an output cycle is started by asserting
DFSO for one DCLKO period. On successive leading edges of DCLKO, the filter output data is shifted out MSB first
on DOUT0 (and DOUT1 for MODE = 1), as shown in the timing diagrams. The spacing of the DFSO pulses depends
on two settings: the overall decimation ratio R of the DDC and the factor DIV. The number of bits which need to be
transmitted in one frame, NBITS, is 64 for MODE = 0 and 32 for MODE = 1. In order to have enough DCLKO cycles
between DFSO pulses, the following relationship must be true:
R
2
DIV
or
NBITS
DIV
log
2
R
NBITS
For example, assume the overall decimation ratio, R, for the DDC is 80. For MODE = 0, the largest allowable value
for DIV is 0. In other words, if MCLK is 80MHz, for R = 80, DCLKO must be 80MHz so that all of the 64 data bits may
be clocked out before the next I and Q data words must be clocked out.
For MODE = 1, since only 32 bits need to be clocked out during one cycle, DCLKO can be reduced to 40MHz (which
means that DIV may be increased to 1, cutting the frequency of DCLKO in half).
DFSI and DIN are used to send control DAC data to the AFE8201. DCLKO supplied by the AFE8201 is used as the
serial clock. An input cycle is initiated by holding DFSI high through one rising edge of DCLKO. On the successive
16 leading edges of DCLKO the input data word is read in serially, MSB first. The lower 12 bits of the data word are
sent to the DAC as the unsigned DAC input.
Note that the input data does not need to bear any timing relationship to the output data, except that both data streams
are synchronous with DCLKO.
QUADRATURE MIXER/NCO
The NCO frequency and initial phase are set by the 32-bit unsigned variables FREQ and PHASE. Each of these
variables is set via a pair of control registers; see Figure 14. The I and Q outputs of the mixer are given by:
I
ADC
sin(2
ft
and
Q
ADC
cos(2
ft
)
)
where
ADC is the output of the IF A/D converter, f is the NCO frequency given by:
f
f
MCLK
FREQ
2
32
and
φ
is the NCO phase offset (in radians) given by:
2PHASE
2
32
P
(2)
(3)
(4)
(5)
(6)
(7)
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