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參數(shù)資料
| 型號： | AFE8201PFBR |
| 英文描述： | IF Analog-to-Digital Converter with Digital Downconverter |
| 中文描述： | 中頻模擬到數(shù)字轉(zhuǎn)換器與數(shù)字下變頻器 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 220K |
| 代理商： | AFE8201PFBR |
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SBWS016A OCTOBER 2003 REVISED JANUARY 2005
www.ti.com
15
For example, using the ODD mode in the first cycle of MCLK, the filter coefficient at BASE_ADDR is applied to two
values in data memory, the most recent at address N and the oldest at address N+10. In the next cycle of MCLK the
coefficient at BASE_ADDR+1 is applied to the data values at N+1 and N+9, and so on until the last coefficient at
BASE_ADDR+5 is reached. Because this is an odd filter, the final coefficient is applied only to the data value at
address N+5. The full cycle is shown in Table 3.
Table 3. ODD Mode Calculation Example with Six Filter Coefficients
Cycle
1
2
Filter Coefficient Address
BASE_ADDR
BASE_ADDR+1
Applied to Data Address
N and N+10
N+1 and N+9
3
4
5
BASE_ADDR+2
BASE_ADDR+3
BASE_ADDR+4
N+2 and N+8
N+3 and N+7
N+4 and N+6
6
BASE_ADDR+5
N+5
Figure 17 clearly illustrates that the overall filter length is different in different filter mode even if NCOEFF is
unchanged. For NCOEFF = 6, filter length ranges from 6 taps for ARBITRARY mode to 19 taps for HALFBAND mode.
The dc gain of the FIR filter depends on the coefficient values and the filter mode.
For ODD mode and for HALFBAND mode, the dc gain is given by:
GAIN
h
NCOEFF
NCOEFF
1
n
1
2h
n
2
15
1
where h
n
is the
nth
of NCOEFF filter coefficients stored in memory.
For EVEN mode the dc gain is:
GAIN
NCOEFF
n
1
2h
n
2
15
1
while for ARBITRARY mode the gain is:
GAIN
NCOEFF
n
1
h
n
2
15
1
P
(10)
(11)
(12)
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| AFE8201PFBT | 制造商:BB 制造商全稱:BB 功能描述:IF Analog-to-Digital Converter with Digital Downconverter |
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