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參數(shù)資料
| 型號： | AFE8201PFBR |
| 英文描述： | IF Analog-to-Digital Converter with Digital Downconverter |
| 中文描述： | 中頻模擬到數(shù)字轉(zhuǎn)換器與數(shù)字下變頻器 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 220K |
| 代理商： | AFE8201PFBR |
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SBWS016A OCTOBER 2003 REVISED JANUARY 2005
www.ti.com
10
DATA INTERFACE
The data interface consists of six signals:
1.
serial data clock DCLKO;
2.
output frame sync DFSO;
3.
output data line DOUT0;
4.
output data line DOUT1;
5.
input frame sync DFSI; and
6.
input data line DIN.
The decimation filter outputs from the DDC (either IA and QA, or IA, QA, IB, and QB) are multiplexed onto the data
outputs. The control DAC data is shifted into the data input. Control Register 0 programs the functionality of the data
interface, as seen in Figure 11.
0
0
0
0
0
DIV
MODE
Don’t Care
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Register Address
Figure 11. Data Interface Control Register
Two parameters, DIV and MODE, control the data interface and are programmed by register 0. The first parameter
is DIV. The serial data clock, DCLKO, is derived from MCLK in a manner controlled by DIV such that the frequency
of DCLKO is:
f
MCLK
2
DIV
f
DCLKO
where DIV ranges from 0 to 3.
As an example, if MCLK is 80MHz, DCLK0 can be either 80MHz, 40MHz, 20MHz, or 10MHz. DCLK0, of course, must
be fast enough to clock out the I and Q data words generated by the on-chip DDC and filters.
The second parameter is MODE. When MODE is 0, all four DDC outputs are time multiplexed onto DOUT0, as shown
in Figure 12. When MODE is 1, IA and QA outputs are multiplexed onto DOUT0 while IB and QB outputs are
multiplexed onto DOUT1, see Figure 13. If only one set of I/Q outputs is used, MODE 1 is recommended so that data
is output through DOUT0.
DCLKO
DFSO
DOUT0
MSB
LSB
MSB
LSB
QA
IB
QB
IA
DOUT1
DFSI
DIN
DAC
Figure 12. Data Interface Timing for MODE = 0
P
(1)
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| AFE8201PFBT | 制造商:BB 制造商全稱:BB 功能描述:IF Analog-to-Digital Converter with Digital Downconverter |
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