參數(shù)資料
型號: AFE8201PFBR
英文描述: IF Analog-to-Digital Converter with Digital Downconverter
中文描述: 中頻模擬到數(shù)字轉(zhuǎn)換器與數(shù)字下變頻器
文件頁數(shù): 13/20頁
文件大?。?/td> 220K
代理商: AFE8201PFBR
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SBWS016A OCTOBER 2003 REVISED JANUARY 2005
www.ti.com
13
FIRST FIR FILTER
The block following the CIC filter is a decimate-by-two FIR filter with programmable coefficients. MODE sets the type
of filter response—ODD (MODE = 00: symmetric impulse response, odd number of taps), EVEN (MODE = 01:
symmetric impulse response, even number of taps), HALFBAND (MODE = 10), and ARBITRARY (MODE = 11:
non-symmetric impulse response).
The 16-bit wide filter coefficients are stored in memory bank 0. Up to 64 coefficients can be stored in this memory.
Depending on the types of filters desired and the number of taps, coefficients for multiple filter responses may be
stored in the memory bank. The filter response may be changed simply by updating the control register with new
values for MODE, NCOEFF, and BASE_ADDR, as shown in Figure 16.
0
0
0
1
1
BASE_ADDR
Don’t Care
NCOEFF
MODE
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Register Address
Figure 16. First FIR Filter Control Register
NCOEFF defines the number of unique filter coefficients which make up the filter response. BASE_ADDR defines
the memory location where the first filter coefficient is stored. The actual filter length is a function of MODE and
NCOEFF:
Filter length = 2(NCOEFF 1) + 1 for ODD
Filter length = 2NCOEFF for EVEN
Filter length = 4(NCOEFF 1) + 1 for HALFBAND
Filter length = NCOEFF for ARBITRARY
The maximum filter length which can be realized is limited by two factors. First, the number of clock cycles between
successive filter outputs limits the number of coefficients which can be processed to:
NCOEFF
2
DEC_RATE
4
where DEC_RATE is the decimation ration of the CIC filter. Second, the size of the data memory (which stores
incoming data samples) limits filter length to 62 taps.
A filter response is defined by a set of NCOEFF 16-bit filter coefficients stored in memory bank 0 (MEM = 0) starting
at address BASE_ADDR. MODE determines how the coefficients are applied to the samples stored in data memory.
Figure 17 is an example illustrating how the filter coefficients are applied to stored input samples in the various filter
modes with NCOEFF = 6. Because NCOEFF = 6 in this example, six computation cycles are required to calculate
the filter output regardless of the filter mode. The leftmost grouping in Figure 17 represents the six filter coefficients
stored at ascending memory address in the coefficient memory starting at BASE_ADDR. At each computation cycle,
the coefficient being applied to the input data is highlighted.
The leftmost grouping in Figure 17 represents the six filter coefficients stored at ascending memory address in the
coefficient memory starting at BASE_ADDR. At each computation cycle, the coefficient being applied to the input
data is highlighted.
The four groupings on the right in Figure 17 represent the four filter modes: EVEN, ODD, HALFBAND, and
ARBITRARY. In each column, the locations in data memory that are operated on at each computation cycle is shown.
The leftmost data sample in each group is the newest sample, the rightmost sample is the oldest. The chart illustrates
the order in which computation on data occurs. To use the chart, select the filter mode of interest, then move down
the chart through the six computation cycles to understand the sequence of calculations.
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