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參數(shù)資料
| 型號(hào)： | AFE8201 |
| 英文描述： | IF Analog-to-Digital Converter with Digital Downconverter |
| 中文描述： | 中頻模擬到數(shù)字轉(zhuǎn)換器與數(shù)字下變頻器 |
| 文件頁(yè)數(shù)： | 7/20頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | AFE8201 |
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SBWS016A OCTOBER 2003 REVISED JANUARY 2005
www.ti.com
7
DETAILED DESCRIPTION
The AFE8201 consists of a general-purpose, 80MSPS, 12-bit analog-to-digital converter (ADC) with programmable
input range, Digital Downconverter (DDC), and user programmable digital filters with 16-bit coefficients. It is designed
to sample narrowband (up to 2.5MHz) IF signals and digitally mix, filter, and decimate the signals to baseband. The
ADC integrates a programmable gain sample-and-hold amplifier that is variable over gains of 1x to 4x to change the
full-scale input voltage range of the device from 1.0V peak to 0.25V peak. When the gain is changed, two sample
periods may be needed for the output of the ADC to settle to the correct value.
The DDC consists of a digital quadrature mixer followed by a CIC decimation filter and FIR filters (FIR1 and FIR2).
The mixer frequency and initial phase are independently programmed by 32-bit control words. The quadrature mixer
generates I and Q signals, each of which are decimated by the CIC filter. The CIC is a 5th-order Comb filter with a
decimation factor that is programmable over a range of 8 to 1024. Each of the FIR filters adds an additional deciamtion
factor of 2, for a total range of 32 to 4096.
The I and Q signals generated by the quadrature mixer are then passed on to the first FIR filter (FIR1). This
decimate-by-two FIR filter can implement even, odd, halfband, and arbitrary impulse responses. The length of the
filter response is dependent on the decimation factor of the CIC filter and the FIR filter response type, up to a
maximum of 62 taps. Coefficients for multiple filter responses may be stored in the coefficient memory (up to 64
unique coefficients may be stored); responses can be changed by changing a control register to point the filter to a
different section of coefficient memory.
Following the first FIR filter are two parallel decimate-by-two FIR filters (FIR2a and FIR2b). These filters are similar
to the first FIR filter, but have twice the data and coefficient memory and can therefore realize longer filter responses.
The responses of the two filters can be different from each other (with some limitations). In addition, the two filters
can be optionally interleaved to form a single extra-long FIR filter which can realize up to 250 taps.
Control register information, as well as decimation filter coefficients, are written to the AFE8201 through the
industry-standard SPI control interface. The baseband output signals are transported through a high-speed serial interface
that is compatible with the TI C5x/C6x DSP buffered serial ports (McBSP).
The AFE8201 also contains a 12-bit auxiliary digital-to-analog converter (DAC) which can be used for a number of
purposes, including tuner automatic gain control or frequency control. Input data for the DAC may be sent either from
the DSP through the serial data port or from a microcontroller through the SPI control interface.
CONTROL INTERFACE
The AFE8201 uses an SPI slave interface to read and write control data. Control data consists of eleven 16-bit control
registers, as shown in Table 1, and three memory banks (see Table 2). The control registers are used to program
all chip parameters. The memory banks store 16-bit FIR filter coefficient data.
To read and write to control registers and memory banks, data is transferred by a 16-bit instruction followed by 16
bits of data. Memory bank read and write operations also support block transfer. Memory bank block transfer consists
of a 16-bit instruction followed by multiple 16 bit data words.
Table 1. Control Registers
Register Address
0
1
2
Description
Data interface parameters DIV, MODE
NCO frequency (bits 015)
NCO frequency (bits 1631)
3
4
5
NCO Initial Phase (bits 015)
NCO Initial Phase (bits 1631)
CIC Filter Decimation Rate: DEC_RATE
6
7
8
9
CIC Filter Parameters: SCALE, SHIFT
First FIR Filter Parameters: BASE_ADDR, NCOEFF, MODE
Second FIR A Filter Parameters: BASE_ADDR, NCOEFF, MODE
Second FIR B Filter Parameters: BASE_ADDR, NCOEFF, MODE
10
11
12
Setup for the Second FIR
Auxiliary DAC: DAC_DATA
ADC Parameters: GAIN, PWD
P
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| AFE8201PFBR | IF Analog-to-Digital Converter with Digital Downconverter |
| AFE8201PFBT | IF Analog-to-Digital Converter with Digital Downconverter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AFE8201PFBR | 制造商:BB 制造商全稱:BB 功能描述:IF Analog-to-Digital Converter with Digital Downconverter |
| AFE8201PFBT | 制造商:BB 制造商全稱:BB 功能描述:IF Analog-to-Digital Converter with Digital Downconverter |
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