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參數(shù)資料
| 型號(hào)： | AFE1224E |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:18; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-18 RoHS Compliant: No |
| 中文描述： | 2Mbps的，單對(duì)模擬前端 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 137K |
| 代理商： | AFE1224E |
7
AFE1224
received in the first 16 bits of each baud period. The
remaining 32-bit periods are not used for Data In. Data Out
is transmitted during the first 16 bits of the baud period. A
second interpolated value is transmitted in subsequent bits of
the baud period.
txbaudCLK:
The transmit data baud rate, generated by the
DSP. It is 784kHz for T1 or 1168kHz for E1. It may vary
from 32kHz (64kbps) to 1168Hz (2.320Mbps).
tx48xCLK:
The transmit pulse former oversampling sam-
pling clock, generated by the DSP. It is 48x the transmit
symbol rate or 56.064MHz for 1168kHz symbol rate. This
clock should run continuously.
Data In:
This is a 16-bit output data word sent from the DSP
to the AFE. The sixteen bits include tx symbol information
and other control bits, as described below. The data should
be clocked out of the DSP on the falling edge and should be
valid on the rising edge of the tx48xCLK. The AFE1224
reads Data In on the rising edge of the tx48xCLK. The bits
are defined in Table I. Data In is read by the AFE1224
during the first 16 bits periods of each baud period. Only the
first 8 bits are used in the AFE1224. The second 8 bits are
reserved for use in the future products. The remaining 32
bits periods of the baud period are not used for Data In.
Data In Bits
tx enable signal—
This bit controls the tx Symbol definition
bits. If this bit is 0, only a 0 symbol is transmitted regardless
of the state of the tx Symbol definition bits. If this bit is 1,
the tx Symbol definition bits determine the output symbol.
tx Symbol Definition—
These two bits determine the output
2B1Q symbol transmitted.
Rx Gain Settings—
These bits set the gain of the receive
channel programmable gain amplifier.
FIGURE 4. Receive Timing Diagram.
FIGURE 3. Data In Word.
1
MSB
LSB
2
3
1
1
2
2
Power Control
Reserved
Not Used
Loopback
rx Gain
tx Symbol
tx Enable
Data Out
from AFE1224
rx48xCLK
from DSP
rxbaudCLK
from DSP
MSB
Bit 15
LSB
Bit 0
MSB
Bit 15
LSB
Bit 0
Data 1a
t
rx1
Interdata 8 Bits
Data 1
Data 2
Interdata 8 Bits
MSB
Bit 15
2.5ns
48
1
14
15
16
17
23
24
25
26
39
40
47
48
1
2.5ns
2.5ns
2.5ns
t
rx1
A
B
RECEIVE TIMING NOTES: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the
rxbaudCLK can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of
the rxbaudCLK can occur within 4ns (on either side) of any rising edge of rx48xCLK. (3) For all data bits after the MSB
of Data 1, the AFE1224 transfers Data Out on the falling edge of the rx48xCLK. The time from the falling edge of
rx48xCLK until Data Out is stable is t
RX1
.
(4) The AFE1224 transfers the MSB of Data 1 on the falling edge of rxbaudCLK. If the falling edge of rxbaudCLK is
synchronized with the falling edge of rx48xCLK, all of the Data Out bits will be the same width. In any case, the time
from the falling edge of rxbaudCLK until the MSB of Data 1 is stable is t
RX1
.
MIN
3ns
MAX
4.6ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AFE1230 | G.SHDSL ANALOG FRONT-END |
| AFE1230E | G.SHDSL ANALOG FRONT-END |
| AFE1231K | G.SHDSL ANALOG FRONT-END |
| AFE1231KG4 | G.SHDSL ANALOG FRONT-END |
| AFE2124 | Dual HDSL/SDSL ANALOG FRONT END |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFE1224E/1K | 功能描述:IC HDSL ANALOG FRONT END 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AFE1224E-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1224E-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1224E-2/1K | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1230 | 制造商:BB 制造商全稱:BB 功能描述:G.SHDSL ANALOG FRONT-END |
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